cargo fix

src/display.rs

@@ -92,7 +92,7 @@ impl BgMapAttributes {
     }
 
     fn vram_bank_number(&self) -> usize {
-        (((self.0 >> 3) & 1) as usize)
+        ((self.0 >> 3) & 1) as usize
     }
 
     fn horizontal_flip(&self) -> bool {
@@ -374,7 +374,7 @@ impl Display {
             }
             0xFF69 => {
                 let idx = self.background_palette_index as usize;
-                if idx < 64  {
+                if idx < 64 {
                     self.background_palette_cgb[idx / 8].0[idx % 8] = val;
                 } else {
                     panic!("OOB palette w/ autoinc");
@@ -389,7 +389,7 @@ impl Display {
             }
             0xFF6B => {
                 let idx = self.object_palette_index as usize;
-                if idx < 64  {
+                if idx < 64 {
                     self.object_palette_cgb[idx / 8].0[idx % 8] = val;
                 } else {
                     panic!("OOB obj palette w/ autoinc");
@@ -459,7 +459,10 @@ impl Display {
             background_map + ((tile_index_y as usize) * 32) + tile_index_x as usize;
             */
         // Background attributes are only in this memory range.
-        assert!(vram_offset >= 0x1800 && vram_offset < 0x2000, format!("offset: {:04X}", vram_offset));
+        assert!(
+            vram_offset >= 0x1800 && vram_offset < 0x2000,
+            format!("offset: {:04X}", vram_offset)
+        );
 
         BgMapAttributes(self.vram1[vram_offset])
     }
@@ -670,7 +673,12 @@ impl Display {
                             continue;
                         }
                         let c = self.object_palette_cgb[sprite.palette() as usize].get_color(c);
-                        self.set_pixel(x.wrapping_add(x_maybe_flipped), render_y, c, PixelOrigin::Sprite);
+                        self.set_pixel(
+                            x.wrapping_add(x_maybe_flipped),
+                            render_y,
+                            c,
+                            PixelOrigin::Sprite,
+                        );
                     }
                 }
             }
@@ -690,8 +698,12 @@ impl Display {
     }
 
     pub fn dump_vram(&self) {
-        std::fs::File::create("vram0.dat").unwrap().write_all(&self.vram0);
-        std::fs::File::create("vram1.dat").unwrap().write_all(&self.vram1);
+        std::fs::File::create("vram0.dat")
+            .unwrap()
+            .write_all(&self.vram0);
+        std::fs::File::create("vram1.dat")
+            .unwrap()
+            .write_all(&self.vram1);
     }
 
     #[inline]

src/interconnect.rs

@@ -397,19 +397,21 @@ impl Interconnect {
                 let mut dst: u16 = ((self.vram_dma_destination_high as u16) << 8)
                     | self.vram_dma_destination_low as u16;
 
+                dst &= 0b0001_1111_1111_0000;
                 dst += 0x8000;
                 println!(
                     "VRAM DMA transfer from {:04X} to {:04X}; {:02X}",
                     src, dst, val
                 );
-                let len: u16 = ((val & 0x7F) + 1) as u16 * 0x10 - 1;
+                let len: u16 = ((val & 0x7F) + 1) as u16 * 0x10;
+                let _mode = val & 0x80 != 0;
                 for i in 0..len {
                     let v = self.read_byte(src.wrapping_add(i));
                     self.write_byte(dst.wrapping_add(i), v);
                 }
 
                 // DMA done
-                self.vram_dma_length = val | 0x80;
+                self.vram_dma_length = 0xFF; // val | 0x80;
             }
             0xFF56 => {
                 self.infrared_com_port = val;

src/mbc/mbc5.rs

@@ -67,10 +67,13 @@ impl MBC for MBC5 {
 
     fn write_byte(&mut self, addr: u16, val: u8) {
         match addr {
-            0x0000..=0x1FFF => match val {
+            0x0000..=0x1FFF => match val & 0x0F {
                 0x0A => self.ram_rtc_enabled = true,
                 0x00 => self.ram_rtc_enabled = false,
-                _ => println!("MBC5: Unknown MBC value {:02X} for {:04X}", val, addr),
+                _ => {
+                    println!("MBC5: Unknown MBC value {:02X} for {:04X}", val, addr);
+                    self.ram_rtc_enabled = false;
+                }
             },
             // Lower part rom bank select
             0x2000..=0x2FFF => self.rom_bank_no = (self.rom_bank_no & (!0xFF)) | u16::from(val),

src/timer.rs

@@ -17,7 +17,7 @@ pub struct Timer {
 // [2] =  4 = 65536  Hz
 // [3] = 16 = 16384  Hz
 const TIMER_SPEED: [u16; 4] = [64, 1, 4, 16];
-const TIMER_ENABLE: u8 = (1 << 2);
+const TIMER_ENABLE: u8 = 1 << 2;
 
 impl Timer {
     pub fn new() -> Timer {