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Improve DMA & MBC5

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This commit is contained in:
Kevin Hamacher 2020-02-18 16:29:05 +01:00
parent 2bbcba2152
commit 55373a6948
2 changed files with 9 additions and 4 deletions
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6
src/interconnect.rs
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@ -397,19 +397,21 @@ impl Interconnect {
let mut dst: u16 = ((self.vram_dma_destination_high as u16) << 8)
| self.vram_dma_destination_low as u16;
dst &= 0b0001_1111_1111_0000;
dst += 0x8000;
println!(
"VRAM DMA transfer from {:04X} to {:04X}; {:02X}",
src, dst, val
);
let len: u16 = ((val & 0x7F) + 1) as u16 * 0x10 - 1;
let len: u16 = ((val & 0x7F) + 1) as u16 * 0x10;
let mode = val & 0x80 != 0;
for i in 0..len {
let v = self.read_byte(src.wrapping_add(i));
self.write_byte(dst.wrapping_add(i), v);
}
// DMA done
self.vram_dma_length = val | 0x80;
self.vram_dma_length = 0xFF; // val | 0x80;
}
0xFF56 => {
self.infrared_com_port = val;

7
src/mbc/mbc5.rs
View File

@ -67,10 +67,13 @@ impl MBC for MBC5 {
fn write_byte(&mut self, addr: u16, val: u8) {
match addr {
0x0000..=0x1FFF => match val {
0x0000..=0x1FFF => match (val & 0x0F) {
0x0A => self.ram_rtc_enabled = true,
0x00 => self.ram_rtc_enabled = false,
_ => println!("MBC5: Unknown MBC value {:02X} for {:04X}", val, addr),
_ => {
println!("MBC5: Unknown MBC value {:02X} for {:04X}", val, addr);
self.ram_rtc_enabled = false;
}
},
// Lower part rom bank select
0x2000..=0x2FFF => self.rom_bank_no = (self.rom_bank_no & (!0xFF)) | u16::from(val),