cargo fix

src/display.rs

@@ -92,7 +92,7 @@ impl BgMapAttributes {
     }
 
     fn vram_bank_number(&self) -> usize {
-        (((self.0 >> 3) & 1) as usize)
+        ((self.0 >> 3) & 1) as usize
     }
 
     fn horizontal_flip(&self) -> bool {

src/interconnect.rs

@@ -404,7 +404,7 @@ impl Interconnect {
                     src, dst, val
                 );
                 let len: u16 = ((val & 0x7F) + 1) as u16 * 0x10;
-                let mode = val & 0x80 != 0;
+                let _mode = val & 0x80 != 0;
                 for i in 0..len {
                     let v = self.read_byte(src.wrapping_add(i));
                     self.write_byte(dst.wrapping_add(i), v);

src/mbc/mbc5.rs

@@ -67,7 +67,7 @@ impl MBC for MBC5 {
 
     fn write_byte(&mut self, addr: u16, val: u8) {
         match addr {
-            0x0000..=0x1FFF => match (val & 0x0F) {
+            0x0000..=0x1FFF => match val & 0x0F {
                 0x0A => self.ram_rtc_enabled = true,
                 0x00 => self.ram_rtc_enabled = false,
                 _ => {

src/timer.rs

@@ -17,7 +17,7 @@ pub struct Timer {
 // [2] =  4 = 65536  Hz
 // [3] = 16 = 16384  Hz
 const TIMER_SPEED: [u16; 4] = [64, 1, 4, 16];
-const TIMER_ENABLE: u8 = (1 << 2);
+const TIMER_ENABLE: u8 = 1 << 2;
 
 impl Timer {
     pub fn new() -> Timer {