106 lines
3.2 KiB
Rust
106 lines
3.2 KiB
Rust
use super::MBC;
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enum BankMode {
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RomBankMode,
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RamBankMode,
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}
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pub struct MBC1 {
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rom: Box<[u8]>,
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ram: Box<[u8]>,
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rom_bank_no: u8,
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bank_mode: BankMode,
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bank_no_high: u8,
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ram_enable: bool,
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}
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impl MBC1 {
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pub fn new(rom: Box<[u8]>, ram: Box<[u8]>) -> MBC1 {
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MBC1 {
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rom,
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ram,
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rom_bank_no: 1,
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bank_mode: BankMode::RomBankMode,
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bank_no_high: 0,
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ram_enable: false,
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}
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}
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fn active_rom_bank(&self) -> u8 {
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match self.bank_mode {
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BankMode::RomBankMode => self.rom_bank_no | (self.bank_no_high << 5),
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BankMode::RamBankMode => self.rom_bank_no,
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}
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}
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fn active_ram_bank(&self) -> u8 {
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match self.bank_mode {
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BankMode::RomBankMode => 0,
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BankMode::RamBankMode => self.bank_no_high,
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}
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}
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}
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impl MBC for MBC1 {
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fn dump_ram(&self, file: &str) {
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super::super::write_file(&file, &self.ram).expect("Saving failed");
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}
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fn read_byte(&self, addr: u16) -> u8 {
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match addr {
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0x0000..=0x3FFF => self.rom[addr as usize],
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0x4000..=0x7FFF => {
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let addr = addr - 0x4000;
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let abs_addr: usize = addr as usize + self.active_rom_bank() as usize * 0x4000;
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let val: u8 = self.rom[abs_addr];
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val
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}
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0xA000..=0xBFFF => {
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let addr = addr - 0xA000;
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println!("Access [{:02X}] {:04X}", self.active_ram_bank(), addr);
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self.ram[self.active_ram_bank() as usize * 0x2000 + addr as usize]
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}
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_ => {
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panic!("MBC1: Unable to read from {:04X}", addr);
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}
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}
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}
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fn write_byte(&mut self, addr: u16, val: u8) {
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match addr {
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0x0000..=0x1FFF => match val {
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0x0A => self.ram_enable = true,
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0x00 => self.ram_enable = false,
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_ => println!("Unknown MBC1 value {:02X} for {:04X}", val, addr),
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},
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0x2000..=0x3FFF => {
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if val != 0 {
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self.rom_bank_no = val & 0x1F;
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} else {
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self.rom_bank_no = 1; // 0x00 -> 0x01, 0x20 -> 0x21 etc
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}
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println!("MBC1: Selecting bank {:02X}", self.rom_bank_no);
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}
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0x4000..=0x5FFF => {
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// Upper ROM bank / RAM bank select
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self.bank_no_high = val & 3;
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}
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0x6000..=0x7FFF => {
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// Select upper ROM bytes or RAM bytes
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match val {
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0 => self.bank_mode = BankMode::RomBankMode,
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1 => self.bank_mode = BankMode::RamBankMode,
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_ => panic!("Invalid bank mode {:02X}", val),
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}
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}
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0xA000..=0xBFFF => {
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let addr = addr - 0xA000;
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println!("Access [{:02X}] {:04X}", self.active_ram_bank(), addr);
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self.ram[self.active_ram_bank() as usize * 0x2000 + addr as usize] = val;
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}
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_ => panic!("MBC1: Writing {:02X} to {:04X} not supported", val, addr),
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}
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}
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}
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