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Fix SRL and SRA

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This commit is contained in:
Kevin Hamacher 2016-05-29 15:13:16 +02:00
parent 4a1b335887
commit fbffa7dccb
1 changed files with 8 additions and 2 deletions
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10
src/cpu.rs
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@ -209,7 +209,7 @@ impl CPU {
} }
let v: u8 = self.get_8bit_reg(reg_id); let v: u8 = self.get_8bit_reg(reg_id);
self.set_clear_flag(FLAG_C, v & 1 > 0); self.set_clear_flag(FLAG_C, v & 1 > 0);
self.set_8bit_reg(reg_id, v >> 1); self.set_8bit_reg(reg_id, v >> 1 | v & 0x80);
}, },
0x30 ... 0x37 => { 0x30 ... 0x37 => {
let reg_id = (instruction - 0x30) as usize; let reg_id = (instruction - 0x30) as usize;
@ -225,8 +225,14 @@ impl CPU {
println!("SRL {}", REG_NAMES[reg_id]); println!("SRL {}", REG_NAMES[reg_id]);
} }
let v: u8 = self.get_8bit_reg(reg_id); let v: u8 = self.get_8bit_reg(reg_id);
self.set_8bit_reg(reg_id, v << 1); self.set_8bit_reg(reg_id, v >> 1);
self.set_clear_flag(FLAG_C, v & 1);
self.clear_flag(FLAG_N);
self.clear_flag(FLAG_H);
self.set_clear_flag(FLAG_Z, (v & 0xFE) == 0);
}, },
// Bits
0x40 ... 0x47 => { 0x40 ... 0x47 => {
// Test 0th bit // Test 0th bit
let reg_id = (instruction - 0x40) as usize; let reg_id = (instruction - 0x40) as usize;