From fbffa7dccbda365b0add6740912c207a540bbd82 Mon Sep 17 00:00:00 2001
From: Kevin Hamacher <kevin.hamacher@ruhr-uni-bochum.de>
Date: Sun, 29 May 2016 15:13:16 +0200
Subject: [PATCH] Fix SRL and SRA

---
 src/cpu.rs | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/cpu.rs b/src/cpu.rs
index 1469826..e8c8ba3 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -209,7 +209,7 @@ impl CPU {
                 }
                 let v: u8 = self.get_8bit_reg(reg_id);
                 self.set_clear_flag(FLAG_C, v & 1 > 0);
-                self.set_8bit_reg(reg_id, v >> 1);
+                self.set_8bit_reg(reg_id, v >> 1 | v & 0x80);
             },
             0x30 ... 0x37 => {
                 let reg_id = (instruction - 0x30) as usize;
@@ -225,8 +225,14 @@ impl CPU {
                     println!("SRL {}", REG_NAMES[reg_id]);
                 }
                 let v: u8 = self.get_8bit_reg(reg_id);
-                self.set_8bit_reg(reg_id, v << 1);
+                self.set_8bit_reg(reg_id, v >> 1);
+                self.set_clear_flag(FLAG_C, v & 1);
+                self.clear_flag(FLAG_N);
+                self.clear_flag(FLAG_H);
+                self.set_clear_flag(FLAG_Z, (v & 0xFE) == 0);
             },
+
+            // Bits
             0x40 ... 0x47 => {
                 // Test 0th bit
                 let reg_id = (instruction - 0x40) as usize;