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Fix RR and RRC

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This commit is contained in:
Kevin Hamacher 2016-05-29 15:16:44 +02:00
parent fbffa7dccb
commit 9040214b85
1 changed files with 3 additions and 9 deletions
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12
src/cpu.rs
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@ -134,8 +134,8 @@ impl CPU {
println!("RRC {}", REG_NAMES[reg_id]); println!("RRC {}", REG_NAMES[reg_id]);
} }
self.set_clear_flag(FLAG_C, val & 1 == 1);
if val & 1 > 0 { if val & 1 > 0 {
self.set_flag(FLAG_C);
self.set_8bit_reg(reg_id, val >> 1 | 0x80); self.set_8bit_reg(reg_id, val >> 1 | 0x80);
} else { } else {
self.set_8bit_reg(reg_id, val >> 1); self.set_8bit_reg(reg_id, val >> 1);
@ -177,17 +177,11 @@ impl CPU {
} }
let carry = self.flags & FLAG_C > 0; let carry = self.flags & FLAG_C > 0;
self.set_clear_flag(FLAG_C, val & 1 == 1);
if !carry { if !carry {
// No carry before, now we got a carry => set it
if val & 0x80 == 0x80 {
self.set_flag(FLAG_C);
}
self.set_8bit_reg(reg_id, val >> 1); self.set_8bit_reg(reg_id, val >> 1);
} else { } else {
if val & 0x80 == 0 { self.set_8bit_reg(reg_id, val >> 1 | 0x80);
self.clear_flag(FLAG_C);
}
self.set_8bit_reg(reg_id, val >> 1 | 1 << 7);
} }
self.clear_flag(FLAG_Z); self.clear_flag(FLAG_Z);
self.clear_flag(FLAG_N); self.clear_flag(FLAG_N);