From 9040214b85235cada5c5e519b9ab4d84c7e3ad6d Mon Sep 17 00:00:00 2001
From: Kevin Hamacher <kevin.hamacher@ruhr-uni-bochum.de>
Date: Sun, 29 May 2016 15:16:44 +0200
Subject: [PATCH] Fix RR and RRC

---
 src/cpu.rs | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/src/cpu.rs b/src/cpu.rs
index e8c8ba3..5fc4005 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -134,8 +134,8 @@ impl CPU {
                     println!("RRC {}", REG_NAMES[reg_id]);
                 }
 
+                self.set_clear_flag(FLAG_C, val & 1 == 1);
                 if val & 1 > 0 {
-                    self.set_flag(FLAG_C);
                     self.set_8bit_reg(reg_id, val >> 1 | 0x80);
                 } else {
                     self.set_8bit_reg(reg_id, val >> 1);
@@ -177,17 +177,11 @@ impl CPU {
                 }
 
                 let carry = self.flags & FLAG_C > 0;
+                self.set_clear_flag(FLAG_C, val & 1 == 1);
                 if !carry {
-                    // No carry before, now we got a carry => set it
-                    if val & 0x80 == 0x80 {
-                        self.set_flag(FLAG_C);
-                    }
                     self.set_8bit_reg(reg_id, val >> 1);
                 } else {
-                    if val & 0x80 == 0 {
-                        self.clear_flag(FLAG_C);
-                    }
-                    self.set_8bit_reg(reg_id, val >> 1 | 1 << 7);
+                    self.set_8bit_reg(reg_id, val >> 1 | 0x80);
                 }
                 self.clear_flag(FLAG_Z);
                 self.clear_flag(FLAG_N);