From 60d098e83c2528551248729526c30476992adfdd Mon Sep 17 00:00:00 2001 From: Kevin Hamacher Date: Tue, 18 Feb 2020 16:29:59 +0100 Subject: [PATCH] cargo fix --- src/display.rs | 2 +- src/interconnect.rs | 2 +- src/mbc/mbc5.rs | 2 +- src/timer.rs | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/display.rs b/src/display.rs index 2d8f9e3..008e0d1 100644 --- a/src/display.rs +++ b/src/display.rs @@ -92,7 +92,7 @@ impl BgMapAttributes { } fn vram_bank_number(&self) -> usize { - (((self.0 >> 3) & 1) as usize) + ((self.0 >> 3) & 1) as usize } fn horizontal_flip(&self) -> bool { diff --git a/src/interconnect.rs b/src/interconnect.rs index 7e5f144..5c3781b 100644 --- a/src/interconnect.rs +++ b/src/interconnect.rs @@ -404,7 +404,7 @@ impl Interconnect { src, dst, val ); let len: u16 = ((val & 0x7F) + 1) as u16 * 0x10; - let mode = val & 0x80 != 0; + let _mode = val & 0x80 != 0; for i in 0..len { let v = self.read_byte(src.wrapping_add(i)); self.write_byte(dst.wrapping_add(i), v); diff --git a/src/mbc/mbc5.rs b/src/mbc/mbc5.rs index 4df4c25..806a43e 100644 --- a/src/mbc/mbc5.rs +++ b/src/mbc/mbc5.rs @@ -67,7 +67,7 @@ impl MBC for MBC5 { fn write_byte(&mut self, addr: u16, val: u8) { match addr { - 0x0000..=0x1FFF => match (val & 0x0F) { + 0x0000..=0x1FFF => match val & 0x0F { 0x0A => self.ram_rtc_enabled = true, 0x00 => self.ram_rtc_enabled = false, _ => { diff --git a/src/timer.rs b/src/timer.rs index 78c9802..de30cee 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -17,7 +17,7 @@ pub struct Timer { // [2] = 4 = 65536 Hz // [3] = 16 = 16384 Hz const TIMER_SPEED: [u16; 4] = [64, 1, 4, 16]; -const TIMER_ENABLE: u8 = (1 << 2); +const TIMER_ENABLE: u8 = 1 << 2; impl Timer { pub fn new() -> Timer {