112 lines
3.6 KiB
Rust
112 lines
3.6 KiB
Rust
use super::MBC;
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pub struct MBC3 {
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rom: Box<[u8]>,
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ram: Box<[u8]>,
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rom_bank_no: u8,
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ram_bank_no: u8,
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ram_rtc_enabled: bool,
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}
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impl MBC3 {
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pub fn new(rom: Box<[u8]>, ram: Box<[u8]>) -> MBC3 {
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MBC3 {
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rom,
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ram,
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rom_bank_no: 1,
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ram_bank_no: 0,
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ram_rtc_enabled: false,
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}
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}
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fn active_rom_bank(&self) -> u8 {
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self.rom_bank_no
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}
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fn active_ram_bank(&self) -> u8 {
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self.ram_bank_no
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}
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}
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impl MBC for MBC3 {
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fn dump_ram(&self, file: &str) {
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super::super::write_file(&file, &self.ram).expect("Saving failed");
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}
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fn read_byte(&self, addr: u16) -> u8 {
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match addr {
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0x0000..=0x3FFF => self.rom[addr as usize],
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0x4000..=0x7FFF => {
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let addr = addr - 0x4000;
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let abs_addr: usize = addr as usize + self.active_rom_bank() as usize * 0x4000;
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let val: u8 = self.rom[abs_addr];
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val
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}
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0xA000..=0xBFFF => {
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let addr = addr - 0xA000;
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match self.active_ram_bank() {
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0x00..=0x03 => {
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self.ram[self.active_ram_bank() as usize * 0x2000 + addr as usize]
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}
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0x08..=0x0C => {
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// TODO
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println!("MBC3: Ignoring RTC read");
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0
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}
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_ => panic!(
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"MBC3: Accessing unknown RAM bank {:02X}",
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self.active_ram_bank()
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),
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}
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}
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_ => {
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panic!("MBC3: Unable to read from {:04X}", addr);
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}
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}
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}
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fn write_byte(&mut self, addr: u16, val: u8) {
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match addr {
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0x0000..=0x1FFF => match val {
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0x0A => self.ram_rtc_enabled = true,
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0x00 => self.ram_rtc_enabled = false,
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_ => println!("MBC3: Unknown MBC value {:02X} for {:04X}", val, addr),
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},
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0x2000..=0x3FFF => self.rom_bank_no = val & 0x7F,
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0x4000..=0x5FFF => {
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// RAM bank select
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match val {
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0x00..=0x03 => self.ram_bank_no = val,
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0x08..=0x0C => self.ram_bank_no = val,
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_ => panic!("MBC3: Unknown RAM bank {:02X}", val),
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}
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}
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0x6000..=0x7FFF => {
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// Latch clock data
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match val {
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0x00 => println!("latch = 0"),
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0x01 => println!("latch = 1"), // TODO: This should copy the current clock to the register
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_ => panic!("MBC3: Unknown latch value {:02X}", val),
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}
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}
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0xA000..=0xBFFF => {
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let addr = addr - 0xA000;
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match self.active_ram_bank() {
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0x00..=0x03 => {
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let active_bank = self.active_ram_bank() as usize;
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self.ram[active_bank * 0x2000 + addr as usize] = val;
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}
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0x08..=0x0C => {
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// TODO
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println!("MBC3: Ignoring RTC write ({:02X})", val);
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}
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_ => panic!(
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"MBC3: Writing unknown RAM bank {:02X}",
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self.active_ram_bank()
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),
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}
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}
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_ => panic!("MBC3: Writing {:02X} to {:04X} not supported", val, addr),
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}
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}
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}
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