227 lines
7.3 KiB
Rust
227 lines
7.3 KiB
Rust
#[derive(Debug,PartialEq)]
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enum MemoryBankControllerType {
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None,
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MBC1,
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MBC2,
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MBC3,
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HuC1,
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}
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#[derive(Debug)]
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enum RamSize {
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None,
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Ram2KB,
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Ram8KB,
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Ram32KB,
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}
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pub struct Cartridge {
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rom: Box<[u8]>,
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ram: Box<[u8]>,
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bank_no: u8,
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mbc_type: MemoryBankControllerType,
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ram_rtc_enabled: bool,
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ram_bank_no: u8,
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ram_size: RamSize,
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rom_banks: u16,
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bank_mode: u8,
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bank_no_high: u8,
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}
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impl Cartridge {
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pub fn new(rom: Box<[u8]>) -> Cartridge {
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let mbc: MemoryBankControllerType = match rom[0x0147] {
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0x00 | 0x08 ... 0x09 => MemoryBankControllerType::None,
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0x01 ... 0x03 => MemoryBankControllerType::MBC1,
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0x05 ... 0x06 => MemoryBankControllerType::MBC2,
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0x0F ... 0x13 => MemoryBankControllerType::MBC3,
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0xFF => MemoryBankControllerType::HuC1,
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_ => panic!("Unsupported MBC type: {:02X}", rom[0x0147]),
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};
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println!("MBC Type: {:?}", &mbc);
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let rom_banks: u16 = match rom[0x0148] {
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0x00 => 0,
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0x01 ... 0x07 => 2u16.pow(rom[0x0148] as u32 + 1),
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0x52 => 72,
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0x53 => 80,
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0x54 => 96,
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_ => panic!("Unknown rom size: {:?}", rom[0x148])
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};
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let ram_size: RamSize = match rom[0x0149] {
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0x00 => RamSize::None,
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0x01 => RamSize::Ram2KB,
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0x02 => RamSize::Ram8KB,
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0x03 => RamSize::Ram32KB,
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_ => panic!("Unknown ram size: {:?}", rom[0x149])
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};
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println!("Rom size: {} banks", rom_banks);
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println!("Ram size: {:?}", ram_size);
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let ram = match ram_size {
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RamSize::None => vec![0u8; 0].into_boxed_slice(),
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RamSize::Ram2KB => vec![0u8; 2048].into_boxed_slice(),
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RamSize::Ram8KB => vec![0u8; 4 * 2048].into_boxed_slice(),
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RamSize::Ram32KB => vec![0u8; 16 * 2048].into_boxed_slice(),
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};
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Cartridge {
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rom: rom,
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mbc_type: mbc,
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bank_no: 1,
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ram_rtc_enabled: false,
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ram_bank_no: 0,
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ram_size: ram_size,
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rom_banks: rom_banks,
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ram: ram,
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bank_mode: 0,
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bank_no_high: 0,
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}
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}
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pub fn read_byte_mbc3(&self, addr: u16) -> u8 {
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match addr {
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0x0000 ... 0x3FFF => self.rom[addr as usize],
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0x4000 ... 0x7FFF => {
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let addr = addr - 0x4000;
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println!("BankNo: {:02X}", self.bank_no);
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let abs_addr: usize = addr as usize + self.bank_no as usize * 0x4000;
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let val: u8 = self.rom[abs_addr];
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val
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},
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0xA000 ... 0xBFFF => {
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// TODO: Safty checks? Or let rust handle this?
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let addr = addr - 0xA000;
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if self.ram_bank_no < 4 {
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self.ram[self.ram_bank_no as usize * 0x2000 + addr as usize]
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} else {
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println!("Ignoring RTC read");
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0
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}
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}
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_ => {
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panic!("Cartride: Unable to read from {:04X}", addr);
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}
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}
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}
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pub fn read_byte_mbc1(&self, addr: u16) -> u8 {
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match addr {
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0x0000 ... 0x3FFF => self.rom[addr as usize],
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0x4000 ... 0x7FFF => {
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let addr = addr - 0x4000;
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let mut bank: u8 = self.bank_no;
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if self.bank_mode == 0 {
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bank |= self.bank_no_high << 5;
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}
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println!("BankNo: {:02X}", bank);
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let abs_addr: usize = addr as usize + bank as usize * 0x4000;
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let val: u8 = self.rom[abs_addr];
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val
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},
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0xA000 ... 0xBFFF => {
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// TODO: Safty checks? Or let rust handle this?
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let addr = addr - 0xA000;
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let mut bank: u8 = 0;
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if self.bank_mode == 1 {
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bank = self.bank_no_high
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}
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self.ram[bank as usize * 0x2000 + addr as usize]
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}
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_ => {
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panic!("Cartride: Unable to read from {:04X}", addr);
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}
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}
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}
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pub fn read_byte(&self, addr: u16) -> u8{
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match self.mbc_type {
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MemoryBankControllerType::MBC1 => self.read_byte_mbc1(addr),
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MemoryBankControllerType::MBC3 | MemoryBankControllerType::None => self.read_byte_mbc3(addr),
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_ => panic!("MBC not supported.")
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}
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}
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fn write_byte_none(&mut self, addr: u16, val: u8) {
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match addr {
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0xA000 ... 0xBFFF => {
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// self.ram[addr as usize - 0xA000] = val;
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println!("No MBC, ignoring RAM write {:02X} to {:04X}", val, addr);
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}
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_ => println!("No MBC, unable to write {:02X} to {:04X}", val, addr),
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}
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}
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fn write_byte_mbc1(&mut self, addr: u16, val: u8) {
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match addr {
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0x2000 ... 0x3FFF => {
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// Write low bits of addr.
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self.bank_no &= 0xE0;
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self.bank_no |= val & 0x1F;
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// Can't select 0x00, 0x20, 0x40, 0x60. Adapt it to 0x01, 0x21, 0x41, 0x61
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if self.bank_no & 0x1F == 0 {
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self.bank_no |= 1;
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}
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}
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0x4000 ... 0x5FFF => {
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self.bank_no_high = val & 3;
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}
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0x6000 ... 0x7FFF => {
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self.bank_mode = val & 1;
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}
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_ => panic!("MBC1 Write {:02X} to {:04X} unsupported", val, addr),
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}
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}
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fn write_byte_mbc3(&mut self, addr: u16, val: u8) {
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match addr {
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0x0000 ... 0x1FFF => {
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match val {
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0x0A => self.ram_rtc_enabled = true,
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0x00 => self.ram_rtc_enabled = false,
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_ => println!("Unknown MBC value {:02X} for {:04X}", val, addr)
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}
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},
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0x2000 ... 0x3FFF => self.bank_no = val & 0x7F,
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0x4000 ... 0x5FFF => {
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// RAM bank select
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match val {
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0x00 ... 0x03 => self.ram_bank_no = val,
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0x08 ... 0x0C => self.ram_bank_no = val, // RTC clock values, TODO
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_ => panic!("Unknown MBC3 RAM BANK NO: {:02X}", val)
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}
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},
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0x6000 ... 0x7FFF => {
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// Latch clock data, ignore.
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},
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0xA000 ... 0xBFFF => {
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// TODO: Safty checks? Or let rust handle this?
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let addr = addr - 0xA000;
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if self.ram_bank_no < 4 {
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self.ram[self.ram_bank_no as usize * 0x2000 + addr as usize] = val;
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} else {
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println!("Ignoring RTC write");
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}
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}
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_ => panic!("MBC3: Writing {:02X} to {:04X} not supported", val, addr),
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}
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}
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pub fn write_byte(&mut self, addr: u16, val: u8) {
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match self.mbc_type {
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MemoryBankControllerType::None => self.write_byte_none(addr, val),
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MemoryBankControllerType::MBC1 => self.write_byte_mbc1(addr, val),
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MemoryBankControllerType::MBC3 => self.write_byte_mbc3(addr, val),
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_ => panic!("MBC not supported.")
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}
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}
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}
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