From f10744b2a603a2581c7674c17a0acb923eb1531e Mon Sep 17 00:00:00 2001
From: Kevin Hamacher <kevin.hamacher@rub.de>
Date: Sat, 28 May 2016 10:18:12 +0200
Subject: [PATCH] RL instruction fix; Nintendo logo correct

---
 src/cpu.rs | 52 ++++++++++++++++++++++++++--------------------------
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/src/cpu.rs b/src/cpu.rs
index 2363c1f..ee00266 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -106,15 +106,15 @@ impl CPU {
                 let carry = self.flags & FLAG_C > 0;
                 if !carry {
                     // No carry before, now we got a carry => set it
-                    if self.regs[REG_A] & 0x80 == 0x80 {
+                    if val & 0x80 == 0x80 {
                         self.set_flag(FLAG_C);
                     }
-                    self.regs[REG_A] = val << 1;
+                    self.set_8bit_reg(reg_id, val << 1);
                 } else {
-                    if self.regs[REG_A] & 0x80 == 0 {
+                    if val & 0x80 == 0 {
                         self.clear_flag(FLAG_C);
                     }
-                    self.regs[REG_A] = val << 1 | 1;
+                    self.set_8bit_reg(reg_id, val << 1 | 1);
                 }
                 self.clear_flag(FLAG_Z);
                 self.clear_flag(FLAG_N);
@@ -231,13 +231,12 @@ impl CPU {
     }
 
     fn get_pair_value(&self, a: usize, b: usize) -> u16 {
-        // TODO: use get_8bit_value / set_8bit_value
-        (self.regs[a] as u16) << 8 | (self.regs[b] as u16)
+        (self.get_8bit_reg(a) as u16) << 8 | self.get_8bit_reg(b) as u16
     }
 
     fn set_pair_value(&mut self, a: usize, b: usize, value: u16) {
-        self.regs[a] = (value >> 8) as u8;
-        self.regs[b] = value as u8;
+        self.set_8bit_reg(a, (value >> 8) as u8);
+        self.set_8bit_reg(b, value as u8);
     }
 
     fn dump_stack(&self) {
@@ -352,6 +351,16 @@ impl CPU {
         4
     }
 
+    fn ld_dref_rr_a(&mut self, r1: usize, r2: usize) -> u8 {
+        if self.debug {
+            println!("LD ({}{}), A", REG_NAMES[r1], REG_NAMES[r2]);
+        }
+        let dst: u16 = self.get_pair_value(r1, r2);
+        let val: u8 = self.get_8bit_reg(REG_N_A);
+        self.interconnect.write_byte(dst, val);
+        8
+    }
+
     fn set_flag(&mut self, flag: u8) {
         self.flags |= flag;
     }
@@ -387,15 +396,7 @@ impl CPU {
                 4
             },
             0x01 => self.ld_rr_vv(REG_N_B, REG_N_C),
-            0x02 => {
-                if self.debug {
-                    println!("LD (BC),A");
-                }
-                let addr: u16 = self.get_pair_value(REG_B, REG_C);
-                let val: u8 = self.regs[REG_A];
-                self.interconnect.write_byte(addr, val);
-                8
-            },
+            0x02 => self.ld_dref_rr_a(REG_N_B, REG_N_C),
             0x04 => self.reg_inc(REG_N_B),
             0x05 => self.reg_dec(REG_N_B),
             0x06 => self.ld_r_v(REG_N_B),
@@ -404,15 +405,7 @@ impl CPU {
             0x0D => self.reg_dec(REG_N_C),
             0x0E => self.ld_r_v(REG_N_C),
             0x11 => self.ld_rr_vv(REG_N_D, REG_N_E),
-            0x12 => {
-                if self.debug {
-                    println!("LD (DE),A");
-                }
-                let addr: u16 = self.get_pair_value(REG_D, REG_E);
-                let val: u8 = self.regs[REG_A];
-                self.interconnect.write_byte(addr, val);
-                12
-            },
+            0x12 => self.ld_dref_rr_a(REG_D, REG_E),
             0x13 => self.inc_rr(REG_D, REG_E),
             0x14 => self.reg_inc(REG_N_D),
             0x15 => self.reg_dec(REG_N_D),
@@ -562,6 +555,13 @@ impl CPU {
             0x3C => self.reg_inc(REG_N_A),
             0x3D => self.reg_dec(REG_N_A),
             0x3E => self.ld_r_v(REG_N_A),
+            0x3F => {
+                if self.debug {
+                    println!("CCF");
+                }
+                self.flags ^= FLAG_C;
+                4
+            }
 
             // LDs
             0x40 ... 0x47 => self.ld_r_r(REG_N_B, (instruction - 0x40) as usize),