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Update other rotate/shift instructions

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This commit is contained in:
Kevin Hamacher 2016-05-29 15:19:40 +02:00
parent 9040214b85
commit ecb66dba71
1 changed files with 19 additions and 10 deletions
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29
src/cpu.rs
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@ -116,8 +116,8 @@ impl CPU {
println!("RLC {}", REG_NAMES[reg_id]);
}
self.set_clear_flag(FLAG_C, val & 0x80 == 80);
if val & 0x80 == 0x80 {
self.set_flag(FLAG_C);
self.set_8bit_reg(reg_id, val << 1 | 1);
} else {
self.set_8bit_reg(reg_id, val << 1);
@ -153,16 +153,10 @@ impl CPU {
}
let carry = self.flags & FLAG_C > 0;
self.set_clear_flag(FLAG_C, val & 0x80 == 0x80);
if !carry {
// No carry before, now we got a carry => set it
if val & 0x80 == 0x80 {
self.set_flag(FLAG_C);
}
self.set_8bit_reg(reg_id, val << 1);
} else {
if val & 0x80 == 0 {
self.clear_flag(FLAG_C);
}
self.set_8bit_reg(reg_id, val << 1 | 1);
}
self.clear_flag(FLAG_Z);
@ -220,7 +214,7 @@ impl CPU {
}
let v: u8 = self.get_8bit_reg(reg_id);
self.set_8bit_reg(reg_id, v >> 1);
self.set_clear_flag(FLAG_C, v & 1);
self.set_clear_flag(FLAG_C, v & 1 == 1);
self.clear_flag(FLAG_N);
self.clear_flag(FLAG_H);
self.set_clear_flag(FLAG_Z, (v & 0xFE) == 0);
@ -862,7 +856,22 @@ impl CPU {
0x0C => self.reg_inc(REG_N_C),
0x0D => self.reg_dec(REG_N_C),
0x0E => self.ld_r_v(REG_N_C),
0x0F => panic!("RRCA not implemented."),
0x0F => {
if self.debug {
println!("RRCA");
}
let val = self.regs[REG_A];
self.set_clear_flag(FLAG_C, val & 1 == 1);
if val & 1 == 0 {
self.regs[REG_A] = self.regs[REG_A] >> 1;
} else {
self.regs[REG_A] = self.regs[REG_A] >> 1 | 0x80;
}
self.clear_flag(FLAG_Z);
self.clear_flag(FLAG_N);
self.clear_flag(FLAG_H);
4
}
0x10 => panic!("STOP 0 {:02X} not implemented.", self.load_args(1)[0]),
0x11 => self.ld_rr_vv(REG_N_D, REG_N_E),