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Add commands; Do not panic!

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Errors will be ignored, just to test how far we come
This commit is contained in:
Kevin Hamacher 2016-05-27 16:57:25 +02:00
parent c733c05e38
commit b52347d5c7
4 changed files with 104 additions and 7 deletions
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102
src/cpu.rs
View File

@ -231,6 +231,7 @@ impl CPU {
}
fn get_pair_value(&self, a: usize, b: usize) -> u16 {
// TODO: use get_8bit_value / set_8bit_value
(self.regs[a] as u16) << 8 | (self.regs[b] as u16)
}
@ -263,6 +264,16 @@ impl CPU {
16
}
fn dec_rr(&mut self, r1: usize, r2: usize) -> u8 {
if self.debug {
println!("DEC {}{}", REG_NAMES[r1], REG_NAMES[r2]);
}
let v = self.get_pair_value(r1, r2);
let v = v.wrapping_sub(1);
self.set_pair_value(r1, r2, v);
8
}
fn inc_rr(&mut self, r1: usize, r2: usize) -> u8 {
if self.debug {
println!("INC {}{}", REG_NAMES[r1], REG_NAMES[r2]);
@ -388,6 +399,7 @@ impl CPU {
0x04 => self.reg_inc(REG_N_B),
0x05 => self.reg_dec(REG_N_B),
0x06 => self.ld_r_v(REG_N_B),
0x0B => self.dec_rr(REG_N_B, REG_N_C),
0x0C => self.reg_inc(REG_N_C),
0x0D => self.reg_dec(REG_N_C),
0x0E => self.ld_r_v(REG_N_C),
@ -447,6 +459,7 @@ impl CPU {
self.regs[REG_A] = self.interconnect.read_byte(self.get_pair_value(REG_D, REG_E));
8
},
0x1B => self.dec_rr(REG_N_D, REG_N_E),
0x1C => self.reg_inc(REG_N_E),
0x1D => self.reg_dec(REG_N_E),
0x1E => self.ld_r_v(REG_N_E),
@ -507,9 +520,17 @@ impl CPU {
self.regs[REG_A] = self.interconnect.read_byte(addr);
8
},
0x2B => self.dec_rr(REG_N_H, REG_N_L),
0x2C => self.reg_inc(REG_N_L),
0x2D => self.reg_dec(REG_N_L),
0x2E => self.ld_r_v(REG_N_L),
0x2F => {
if self.debug {
println!("CPL");
}
self.regs[REG_A] = !self.regs[REG_A];
4
},
0x31 => {
let args = self.load_args(2);
self.sp = to_u16(args);
@ -613,6 +634,22 @@ impl CPU {
4
}
// AND
0xA0 ... 0xA7 => {
let reg_id = (instruction - 0xA0) as usize;
if self.debug {
println!("AND {}", REG_NAMES[reg_id]);
}
self.regs[REG_A] &= self.get_8bit_reg(reg_id);
self.clear_flag(FLAG_N);
if self.regs[REG_A] == 0 {
self.set_flag(FLAG_Z);
} else {
self.clear_flag(FLAG_Z);
}
4
}
// XOR
0xA8 ... 0xAF => {
let reg_id = (instruction - 0xA8) as usize;
@ -632,6 +669,22 @@ impl CPU {
4
},
// OR
0xB0 ... 0xB7 => {
let reg_id = (instruction - 0xB0) as usize;
if self.debug {
println!("OR {}", REG_NAMES[reg_id]);
}
self.regs[REG_A] |= self.get_8bit_reg(reg_id);
self.clear_flag(FLAG_N);
if self.regs[REG_A] == 0 {
self.set_flag(FLAG_Z);
} else {
self.clear_flag(FLAG_Z);
}
4
}
// CP
0xB8 ... 0xBF => {
let reg_id = (instruction - 0xB8) as usize;
@ -690,6 +743,14 @@ impl CPU {
}
},
0xC5 => self.push_rr(REG_B, REG_C),
0xC6 => {
let val = self.load_args(1)[0];
if self.debug {
println!("ADD {:02X}", val);
}
self.regs[REG_A] = self.regs[REG_A].wrapping_add(val);
8
},
0xC9 => {
if self.debug {
println!("RET");
@ -730,6 +791,14 @@ impl CPU {
self.ip = target;
24
},
0xD6 => {
let val = self.load_args(1)[0];
if self.debug {
println!("SUB {:02X}", val);
}
self.regs[REG_A] = self.regs[REG_A].wrapping_sub(val);
8
},
0xE0 => {
let args = self.load_args(1);
if self.debug {
@ -738,6 +807,7 @@ impl CPU {
self.interconnect.write_byte(0xFF00 + args[0] as u16, self.regs[REG_A]);
12
},
0xE1 => self.pop_rr(REG_N_H, REG_N_L),
0xE2 => {
if self.debug {
println!("LD (C), A");
@ -746,6 +816,14 @@ impl CPU {
self.interconnect.write_byte(0xFF00 + self.regs[REG_C] as u16, self.regs[REG_A]);
8
},
0xE6 => {
let val = self.load_args(1)[0];
if self.debug {
println!("AND {:02X}", val);
}
self.regs[REG_A] &= val;
8
},
0xEA => {
let addr = to_u16(self.load_args(2));
if self.debug{
@ -753,7 +831,17 @@ impl CPU {
}
self.interconnect.write_byte(addr, self.regs[REG_A]);
16
}
},
0xEF => {
// Make sure this is correct.
if self.debug {
println!("RST 0x28");
}
self.interconnect.write_word(self.sp - 1, self.ip);
self.sp -= 2;
self.ip = 0x28;
16
},
0xF0 => {
let args = self.load_args(1);
if self.debug {
@ -775,14 +863,22 @@ impl CPU {
}
self.interrupts_enabled = false;
4
}
},
0xF6 => {
let val = self.load_args(1)[0];
if self.debug {
println!("OR {:02X}", val);
}
self.regs[REG_A] |= val;
8
},
0xFB => {
// Enable interrupts - TODO
if self.debug {
println!("EI");
}
self.interrupts_enabled = true;
panic!("ENABLING INTERRUPTS - TODO");
println!("ENABLING INTERRUPTS - TODO");
4
},
0xFE => {

4
src/display.rs
View File

@ -189,7 +189,7 @@ impl Display {
let render_y: u8 = self.curline;
if self.control & CTRL_BG_SPRITE_ENABLE > 0 {
panic!("Sprites not supported");
// panic!("Sprites not supported");
}
// Render background
@ -234,7 +234,7 @@ impl Display {
// This set goes from -127 to 127.
let s_tid: i8 = tile_id as i8;
tile_id = (128u8 as i8 + s_tid) as u8;
panic!("OH MY GOD, this wasn't tested yet");
// panic!("OH MY GOD, this wasn't tested yet");
}
let tile_base_addr: usize = tile_base_addr + (tile_id as usize) * 16;

3
src/interconnect.rs
View File

@ -111,6 +111,7 @@ impl Interconnect {
0xC000 ... 0xDFFF => {
self.ram[(addr - 0xC000) as usize]
},
0xFF00 => 0xFF, // TODO: This is the input stuff
0xFF01 ... 0xFF02 => self.serial.read_byte(addr),
0xFF04 ... 0xFF07 => self.timer.read_byte(addr),
0xFF0F => {
@ -185,7 +186,7 @@ impl Interconnect {
self.interrupt = val;
},
_ => {
panic!("Write {:02X} to {:04X} not supported.", val, addr);
println!("Write {:02X} to {:04X} not supported.", val, addr);
}
}
}

2
src/sound.rs
View File

@ -23,7 +23,7 @@ impl Sound {
0xFF24 => self.sound_channel_volume_control = val,
0xFF25 => self.sound_output_terminal_selector = val,
0xFF26 => self.enabled = val,
_ => panic!("Sound: Write {:02X} to {:04X} unsupported", val, addr),
_ => println!("Sound: Write {:02X} to {:04X} unsupported", val, addr),
}
}