MBC1: Allow writing to RAM

src/mbc/mbc1.rs

@@ -94,6 +94,11 @@ impl MBC for MBC1 {
                     _ => panic!("Invalid bank mode {:02X}", val),
                 }
             }
+            0xA000..=0xBFFF => {
+                let addr = addr - 0xA000;
+                println!("Access [{:02X}] {:04X}", self.active_ram_bank(), addr);
+                self.ram[self.active_ram_bank() as usize * 0x2000 + addr as usize] = val;
+            }
             _ => panic!("MBC1: Writing {:02X} to {:04X} not supported", val, addr),
         }
     }