diff --git a/src/cpu.rs b/src/cpu.rs
index f4a6abd..417395c 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -229,11 +229,9 @@ impl CPU {
                 if self.debug {
                     println!("BIT 0, {}", REG_NAMES[reg_id]);
                 }
-                if reg_content & (1 << 0) == 0 {
-                    self.flags |= FLAG_Z;
-                } else {
-                    self.flags &= !FLAG_Z;
-                }
+                self.set_clear_flag(FLAG_Z, reg_content & (1 << 0) == 0);
+                self.clear_flag(FLAG_N);
+                self.set_flag(FLAG_H);
             }
             0x48 ... 0x4F => {
                 // Test 1th bit
@@ -242,11 +240,9 @@ impl CPU {
                 if self.debug {
                     println!("BIT 1, {}", REG_NAMES[reg_id]);
                 }
-                if reg_content & (1 << 1) == 0 {
-                    self.flags |= FLAG_Z;
-                } else {
-                    self.flags &= !FLAG_Z;
-                }
+                self.set_clear_flag(FLAG_Z, reg_content & (1 << 1) == 0);
+                self.clear_flag(FLAG_N);
+                self.set_flag(FLAG_H);
             }
             0x50 ... 0x57 => {
                 // Test 2th bit
@@ -255,11 +251,9 @@ impl CPU {
                 if self.debug {
                     println!("BIT 2, {}", REG_NAMES[reg_id]);
                 }
-                if reg_content & (1 << 2) == 0 {
-                    self.flags |= FLAG_Z;
-                } else {
-                    self.flags &= !FLAG_Z;
-                }
+                self.set_clear_flag(FLAG_Z, reg_content & (1 << 2) == 0);
+                self.clear_flag(FLAG_N);
+                self.set_flag(FLAG_H);
             }
             0x58 ... 0x5F => {
                 // Test 3th bit
@@ -268,11 +262,9 @@ impl CPU {
                 if self.debug {
                     println!("BIT 3, {}", REG_NAMES[reg_id]);
                 }
-                if reg_content & (1 << 3) == 0 {
-                    self.flags |= FLAG_Z;
-                } else {
-                    self.flags &= !FLAG_Z;
-                }
+                self.set_clear_flag(FLAG_Z, reg_content & (1 << 3) == 0);
+                self.clear_flag(FLAG_N);
+                self.set_flag(FLAG_H);
             }
             0x60 ... 0x67 => {
                 // Test 4th bit
@@ -281,11 +273,9 @@ impl CPU {
                 if self.debug {
                     println!("BIT 4, {}", REG_NAMES[reg_id]);
                 }
-                if reg_content & (1 << 4) == 0 {
-                    self.flags |= FLAG_Z;
-                } else {
-                    self.flags &= !FLAG_Z;
-                }
+                self.set_clear_flag(FLAG_Z, reg_content & (1 << 4) == 0);
+                self.clear_flag(FLAG_N);
+                self.set_flag(FLAG_H);
             }
             0x68 ... 0x6F => {
                 // Test 5th bit
@@ -294,11 +284,9 @@ impl CPU {
                 if self.debug {
                     println!("BIT 5, {}", REG_NAMES[reg_id]);
                 }
-                if reg_content & (1 << 5) == 0 {
-                    self.flags |= FLAG_Z;
-                } else {
-                    self.flags &= !FLAG_Z;
-                }
+                self.set_clear_flag(FLAG_Z, reg_content & (1 << 5) == 0);
+                self.clear_flag(FLAG_N);
+                self.set_flag(FLAG_H);
             }
             0x70 ... 0x77 => {
                 // Test 6th bit
@@ -307,11 +295,9 @@ impl CPU {
                 if self.debug {
                     println!("BIT 6, {}", REG_NAMES[reg_id]);
                 }
-                if reg_content & (1 << 6) == 0 {
-                    self.flags |= FLAG_Z;
-                } else {
-                    self.flags &= !FLAG_Z;
-                }
+                self.set_clear_flag(FLAG_Z, reg_content & (1 << 6) == 0);
+                self.clear_flag(FLAG_N);
+                self.set_flag(FLAG_H);
             }
             0x78 ... 0x7F => {
                 // Test 7th bit
@@ -320,11 +306,83 @@ impl CPU {
                 if self.debug {
                     println!("BIT 7, {}", REG_NAMES[reg_id]);
                 }
-                if reg_content & (1 << 7) == 0 {
-                    self.flags |= FLAG_Z;
-                } else {
-                    self.flags &= !FLAG_Z;
+                self.set_clear_flag(FLAG_Z, reg_content & (1 << 7) == 0);
+                self.clear_flag(FLAG_N);
+                self.set_flag(FLAG_H);
+            }
+
+            // Reset bits
+            0x80 ... 0x87 => {
+                // Reset 0th bit
+                let reg_id = (instruction - 0x80) as usize;
+                let reg_content = self.get_8bit_reg(reg_id);
+                if self.debug {
+                    println!("RES 0, {}", REG_NAMES[reg_id]);
                 }
+                self.set_8bit_reg(reg_id, reg_content & !(1 << 0));
+            }
+            0x88 ... 0x8F => {
+                // Reset 1th bit
+                let reg_id = (instruction - 0x88) as usize;
+                let reg_content = self.get_8bit_reg(reg_id);
+                if self.debug {
+                    println!("RES 1, {}", REG_NAMES[reg_id]);
+                }
+                self.set_8bit_reg(reg_id, reg_content & !(1 << 1));
+            }
+            0x90 ... 0x97 => {
+                // Reset 2nd bit
+                let reg_id = (instruction - 0x90) as usize;
+                let reg_content = self.get_8bit_reg(reg_id);
+                if self.debug {
+                    println!("RES 2, {}", REG_NAMES[reg_id]);
+                }
+                self.set_8bit_reg(reg_id, reg_content & !(1 << 2));
+            }
+            0x98 ... 0x9F => {
+                // Reset 3th bit
+                let reg_id = (instruction - 0x98) as usize;
+                let reg_content = self.get_8bit_reg(reg_id);
+                if self.debug {
+                    println!("RES 3, {}", REG_NAMES[reg_id]);
+                }
+                self.set_8bit_reg(reg_id, reg_content & !(1 << 3));
+            }
+            0xA0 ... 0xA7 => {
+                // Reset 4th bit
+                let reg_id = (instruction - 0xA0) as usize;
+                let reg_content = self.get_8bit_reg(reg_id);
+                if self.debug {
+                    println!("RES 4, {}", REG_NAMES[reg_id]);
+                }
+                self.set_8bit_reg(reg_id, reg_content & !(1 << 4));
+            }
+            0xA8 ... 0xAF => {
+                // Reset 5th bit
+                let reg_id = (instruction - 0xA8) as usize;
+                let reg_content = self.get_8bit_reg(reg_id);
+                if self.debug {
+                    println!("RES 5, {}", REG_NAMES[reg_id]);
+                }
+                self.set_8bit_reg(reg_id, reg_content & !(1 << 5));
+            }
+            0xB0 ... 0xB7 => {
+                // Reset 6th bit
+                let reg_id = (instruction - 0xB0) as usize;
+                let reg_content = self.get_8bit_reg(reg_id);
+                if self.debug {
+                    println!("RES 6, {}", REG_NAMES[reg_id]);
+                }
+                self.set_8bit_reg(reg_id, reg_content & !(1 << 6));
+            }
+            0xB8 ... 0xBF => {
+                // Reset 7th bit
+                let reg_id = (instruction - 0xB8) as usize;
+                let reg_content = self.get_8bit_reg(reg_id);
+                if self.debug {
+                    println!("RES 7, {}", REG_NAMES[reg_id]);
+                }
+                self.set_8bit_reg(reg_id, reg_content & !(1 << 7));
             }
             _ => {
                 panic!("Unsupported prefix instruction: {:x}", instruction);