Serial and Timer class, cycle counting
Also a little bit of refactoring. Move VRAM to the display object
This commit is contained in:
Kevin Hamacher
parent
94e73b2eda
commit
396e87304e
151
src/cpu.rs
151
src/cpu.rs
@ -24,6 +24,8 @@ pub struct CPU {
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sp: u16,
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interconnect: interconnect::Interconnect,
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interrupts_enabled: bool,
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}
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fn to_u16(bytes: Box<[u8]>) -> u16 {
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@ -39,7 +41,8 @@ impl CPU {
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regs: [0, 0, 0, 0, 0, 0, 0],
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ip: 0,
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sp: 0xFFFE,
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interconnect: interconnect
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interconnect: interconnect,
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interrupts_enabled: false, // Is this correct?
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}
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}
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@ -234,56 +237,80 @@ impl CPU {
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print!("C={} ", self.flags & FLAG_C != 0);
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self.ip += 1;
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let mut cycles: u16;
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match instruction {
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0x00 => {
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println!("NOP");
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cycles = 4;
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},
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0x01 => {
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println!("LD (BC), A");
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let addr: u16 = self.get_pair_value(REG_B, REG_C);
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let val: u8 = self.regs[REG_A];
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self.interconnect.write_byte(addr, val);
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cycles = 12;
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}
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0x04 => {
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println!("INC B");
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self.reg_inc(REG_B);
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cycles = 4;
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},
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0x05 => {
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println!("DEC B");
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self.reg_dec(REG_B);
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cycles = 4;
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},
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0x06 => {
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let args = self.load_args(1);
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println!("LD B, {:02x}", args[0]);
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self.regs[REG_B] = args[0];
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cycles = 8;
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},
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0x0C => {
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println!("INC C");
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self.reg_inc(REG_C);
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cycles = 4;
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},
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0x0D => {
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println!("DEC C");
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self.reg_dec(REG_C);
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cycles = 4;
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},
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0x0E => {
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let args = self.load_args(1);
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println!("LD C, {:02x}", args[0]);
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self.regs[REG_C] = args[0];
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cycles = 8;
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},
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0x11 => {
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let args = self.load_args(2);
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let val = to_u16(args);
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println!("LD DE, {:04x}", val);
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self.set_pair_value(REG_D, REG_E, val);
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cycles = 12;
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},
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0x13 => {
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println!("INC DE");
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let old_value = self.get_pair_value(REG_D, REG_E);
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self.set_pair_value(REG_D, REG_E, old_value + 1);
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cycles = 8;
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},
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0x14 => {
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println!("INC D");
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self.reg_inc(REG_D);
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cycles = 4;
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},
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0x15 => {
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println!("DEC D");
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self.reg_dec(REG_D);
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cycles = 4;
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},
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0x16 => {
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let args = self.load_args(1);
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println!("LD D, {:02x}", args[0]);
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self.regs[REG_D] = args[0];
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cycles = 8;
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},
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0x17 => {
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println!("RLA");
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@ -300,6 +327,7 @@ impl CPU {
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}
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self.regs[REG_A] = self.regs[REG_A] << 1 | 1;
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}
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cycles = 4;
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},
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0x18 => {
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let args = self.load_args(1);
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@ -310,23 +338,28 @@ impl CPU {
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} else {
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self.ip += off as u16;
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}
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cycles = 12;
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},
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0x1A => {
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println!("LD A, (DE)");
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self.regs[REG_A] = self.interconnect.read_byte(self.get_pair_value(REG_D, REG_E));
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cycles = 8;
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},
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0x1C => {
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println!("INC E");
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self.reg_inc(REG_E);
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cycles = 4;
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},
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0x1D => {
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println!("DEC E");
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self.reg_dec(REG_E);
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cycles = 4;
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},
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0x1E => {
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let args = self.load_args(1);
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println!("LD E, {:02x}", args[0]);
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self.regs[REG_E] = args[0];
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cycles = 8;
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},
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0x20 => {
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let args = self.load_args(1);
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@ -338,36 +371,45 @@ impl CPU {
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} else {
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self.ip += offset as u16;
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}
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cycles = 12;
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} else {
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cycles = 8;
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}
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}
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0x21 => {
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let value = to_u16(self.load_args(2));
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println!("LD HL, {:04x}", value);
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self.set_pair_value(REG_H, REG_L, value);
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cycles = 12;
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},
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0x22 => {
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println!("LD (HL+), A");
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let addr: u16 = self.get_pair_value(REG_H, REG_L);
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self.interconnect.write_byte(addr, self.regs[REG_A]);
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self.set_pair_value(REG_H, REG_L, addr + 1);
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cycles = 8;
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},
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0x23 => {
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println!("INC HL");
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let old_value = self.get_pair_value(REG_H, REG_L);
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self.set_pair_value(REG_H, REG_L, old_value + 1);
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cycles = 8;
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},
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0x24 => {
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println!("INC H");
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self.reg_inc(REG_H);
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cycles = 4;
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},
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0x25 => {
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println!("DEC H");
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self.reg_dec(REG_H);
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cycles = 4;
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},
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0x26 => {
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let args = self.load_args(1);
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println!("LD H, {:02x}", args[0]);
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self.regs[REG_H] = args[0];
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cycles = 8;
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},
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0x28 => {
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let args = self.load_args(1);
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@ -377,26 +419,35 @@ impl CPU {
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} else {
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target = self.ip + args[0] as u16;
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}
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println!("LR Z, {:04X}", target);
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println!("JR Z, {:04X}", target);
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if self.flags & FLAG_Z > 0 {
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self.ip = target;
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cycles = 12;
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} else {
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cycles = 8;
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}
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},
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0x2C => {
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println!("INC L");
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self.reg_inc(REG_L);
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cycles = 4;
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},
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0x2D => {
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println!("DEC L");
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self.reg_dec(REG_L);
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cycles = 4;
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},
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0x2E => {
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let args = self.load_args(1);
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println!("LD L, {:02x}", args[0]);
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self.regs[REG_L] = args[0];
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cycles = 8;
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},
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0x31 => {
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let args = self.load_args(2);
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self.sp = to_u16(args);
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println!("LD SP, {:02x}", self.sp);
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cycles = 12;
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},
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0x32 => {
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println!("LD (HL-), A");
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@ -405,25 +456,30 @@ impl CPU {
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addr -= 1;
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self.set_pair_value(REG_H, REG_L, addr);
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cycles = 8;
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},
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0x36 => {
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let args = self.load_args(1);
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println!("LD (HL), {:02x}", args[0]);
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let addr = self.get_pair_value(REG_H, REG_L);
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self.interconnect.write_byte(addr, args[0]);
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cycles = 12;
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},
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0x3C => {
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println!("INC A");
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self.reg_inc(REG_A);
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cycles = 4;
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}
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0x3D => {
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println!("DEC A");
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self.reg_dec(REG_A);
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cycles = 4;
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}
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0x3E => {
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let args = self.load_args(1);
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println!("LD A, {:02x}", args[0]);
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self.regs[REG_A] = args[0];
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cycles = 8;
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},
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// LDs
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@ -431,37 +487,44 @@ impl CPU {
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let reg_id = (instruction - 0x40) as usize;
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println!("LD B, {}", REG_NAMES[reg_id]);
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self.regs[REG_B] = self.get_8bit_reg(reg_id);
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cycles = 4;
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},
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0x48 ... 0x4F => {
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let reg_id = (instruction - 0x48) as usize;
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println!("LD C, {}", REG_NAMES[reg_id]);
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self.regs[REG_C] = self.get_8bit_reg(reg_id);
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cycles = 4;
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},
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0x50 ... 0x57 => {
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let reg_id = (instruction - 0x50) as usize;
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println!("LD D, {}", REG_NAMES[reg_id]);
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self.regs[REG_D] = self.get_8bit_reg(reg_id);
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cycles = 4;
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},
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0x58 ... 0x5F => {
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let reg_id = (instruction - 0x58) as usize;
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println!("LD E, {}", REG_NAMES[reg_id]);
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self.regs[REG_E] = self.get_8bit_reg(reg_id);
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cycles = 4;
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},
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0x60 ... 0x67 => {
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let reg_id = (instruction - 0x60) as usize;
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println!("LD H, {}", REG_NAMES[reg_id]);
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self.regs[REG_H] = self.get_8bit_reg(reg_id);
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cycles = 4;
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},
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0x68 ... 0x6F => {
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let reg_id = (instruction - 0x68) as usize;
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println!("LD L, {}", REG_NAMES[reg_id]);
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self.regs[REG_L] = self.get_8bit_reg(reg_id);
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cycles = 4;
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},
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0x70 ... 0x75 | 0x77 => {
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let reg_id = (instruction - 0x70) as usize;
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println!("LD (HL), {}", REG_NAMES[reg_id]);
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let reg_value: u8 = self.get_8bit_reg(reg_id);
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let addr: u16 = self.get_pair_value(REG_H, REG_L);
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cycles = 8;
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self.interconnect.write_byte(addr, reg_value);
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},
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@ -469,6 +532,7 @@ impl CPU {
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let reg_id = (instruction - 0x78) as usize;
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println!("LD A, {}", REG_NAMES[reg_id]);
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self.regs[REG_A] = self.get_8bit_reg(reg_id);
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cycles = 4;
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},
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// ADD
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@ -477,6 +541,7 @@ impl CPU {
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println!("ADD {}", REG_NAMES[reg_id]);
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self.regs[REG_A] = self.regs[REG_A].wrapping_add(self.get_8bit_reg(reg_id));
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self.flags &= !FLAG_N;
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cycles = 4;
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}
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// ADC
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@ -488,6 +553,7 @@ impl CPU {
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self.regs[REG_A] = self.regs[REG_A].wrapping_add(1);
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}
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self.flags &= !FLAG_N;
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cycles = 4;
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}
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// SUBs
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@ -502,6 +568,7 @@ impl CPU {
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self.flags &= !FLAG_Z;
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}
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// TODO: H, C
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cycles = 4;
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}
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// SBC
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@ -513,6 +580,7 @@ impl CPU {
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self.regs[REG_A] = self.regs[REG_A].wrapping_sub(1);
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}
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self.flags |= FLAG_N;
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cycles = 4;
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}
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// XOR
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@ -528,6 +596,7 @@ impl CPU {
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self.flags &= !FLAG_C;
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self.flags &= !FLAG_N;
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self.flags &= !FLAG_H;
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cycles = 4;
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},
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// CP
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@ -545,66 +614,127 @@ impl CPU {
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self.flags &= !FLAG_Z;
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self.flags &= !FLAG_C;
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}
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cycles = 4;
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},
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0xC1 => {
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println!("POP BC");
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let val: u16 = self.interconnect.read_word(self.sp);
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self.sp += 2;
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self.set_pair_value(REG_B, REG_C, val);
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cycles = 12;
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},
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0xC2 => {
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let addr: u16 = to_u16(self.load_args(2));
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println!("JP NZ {:04X}", addr);
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if self.flags & FLAG_Z == 0 {
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self.ip = addr;
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cycles = 16;
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} else {
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cycles = 12;
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}
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},
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0xC3 => {
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let addr: u16 = to_u16(self.load_args(2));
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println!("JP {:04X}", addr);
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self.ip = addr;
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cycles = 16;
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}
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0xC4 => {
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let target = to_u16(self.load_args(2));
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println!("CALL NZ {:04X}", &target);
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if self.flags & FLAG_Z == 0 {
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// Push current IP to the stack
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self.interconnect.write_word(self.sp - 1, self.ip);
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self.sp -= 2;
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self.ip = target;
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cycles = 24;
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} else {
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cycles = 12;
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}
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},
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0xC5 => {
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println!("PUSH BC");
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let val: u16 = self.get_pair_value(REG_B, REG_C);
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self.interconnect.write_word(self.sp - 2, val);
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self.sp -= 2;
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cycles = 16;
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},
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0xC9 => {
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println!("RET");
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self.dump_stack();
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self.ip = self.interconnect.read_word(self.sp+1);
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self.sp += 2;
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cycles = 16;
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},
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0xCB => {
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// Prefix CB. This is annoying.
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self.run_prefix_instruction();
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cycles = 12; // TODO: Verify that this is the case for all prefix instructions.
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},
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0xCC => {
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let target = to_u16(self.load_args(2));
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println!("CALL Z {:04X}", &target);
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if self.flags & FLAG_Z > 0 {
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// Push current IP to the stack
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self.interconnect.write_word(self.sp - 1, self.ip);
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self.sp -= 2;
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self.ip = target;
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cycles = 24;
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} else {
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cycles = 12;
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}
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},
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0xCD => {
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let target = to_u16(self.load_args(2));
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println!("CALL {:04X}", &target);
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// Push current IP to the stack
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// self.interconnect.write_byte(self.sp, (self.ip & 0xFF) as u8);
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// self.interconnect.write_byte(self.sp - 1, (self.ip >> 8) as u8);
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self.interconnect.write_word(self.sp - 1, self.ip);
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self.sp -= 2;
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self.dump_stack();
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self.ip = target;
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cycles = 24;
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},
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0xE0 => {
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let args = self.load_args(1);
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println!("LDH {:02X}, A", args[0]);
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self.interconnect.write_byte(0xFF00 + args[0] as u16, self.regs[REG_A]);
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cycles = 12;
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},
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0xE2 => {
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println!("LD (C), A");
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println!("[{:04X}] = {:02X}", 0xFF00 + self.regs[REG_C] as u16, self.regs[REG_A]);
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self.interconnect.write_byte(0xFF00 + self.regs[REG_C] as u16, self.regs[REG_A])
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self.interconnect.write_byte(0xFF00 + self.regs[REG_C] as u16, self.regs[REG_A]);
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cycles = 8;
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},
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0xEA => {
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let addr = to_u16(self.load_args(2));
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println!("LD ({:04X}), A", addr);
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self.interconnect.write_byte(addr, self.regs[REG_A]);
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cycles = 16;
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}
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0xF0 => {
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let args = self.load_args(1);
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println!("LDH A, {:02X}", args[0]);
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self.regs[REG_A] = self.interconnect.read_byte(0xFF00 + args[0] as u16);
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cycles = 12;
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},
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0xF2 => {
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println!("LD A, (C)");
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self.regs[REG_A] = self.interconnect.read_byte(0xFF00 + self.regs[REG_C] as u16);
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cycles = 8;
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},
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0xF3 => {
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println!("DI");
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self.interrupts_enabled = false;
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cycles = 4;
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}
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0xFB => {
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// Enable interrupts - TODO
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println!("EI");
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self.interconnect.write_byte(0xFFFF, 0x01);
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panic!("Uh uh");
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self.interrupts_enabled = true;
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// self.interconnect.write_byte(0xFFFF, 0x01);
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// panic!("Uh uh");
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cycles = 4;
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panic!("ENABLING INTERRUPTS - TODO");
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},
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0xFE => {
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let args = self.load_args(1);
|
||||
@ -622,10 +752,11 @@ impl CPU {
|
||||
}
|
||||
|
||||
// TODO H
|
||||
cycles = 8;
|
||||
}
|
||||
_ => panic!("Unknown instruction: {:02x}", instruction)
|
||||
}
|
||||
// self.dump_stack();
|
||||
self.interconnect.tick();
|
||||
self.interconnect.tick(cycles);
|
||||
}
|
||||
}
|
||||
|
||||
118
src/display.rs
118
src/display.rs
@ -1,43 +1,159 @@
|
||||
const VRAM_SIZE: usize = 0x2000;
|
||||
|
||||
const TICKS_END_SCANLINE: u16 = 80;
|
||||
const TICKS_END_READMODE: u16 = 172;
|
||||
const TICKS_END_HBLANK: u16 = 204;
|
||||
const TICKS_END_VBLANK: u16 = 456;
|
||||
|
||||
#[derive(Debug)]
|
||||
enum DisplayMode {
|
||||
Scanline,
|
||||
Readmode,
|
||||
HBlank,
|
||||
VBlank,
|
||||
}
|
||||
|
||||
impl Default for DisplayMode {
|
||||
fn default() -> DisplayMode {
|
||||
DisplayMode::Scanline
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Default)]
|
||||
pub struct Display {
|
||||
control: u8,
|
||||
status: u8,
|
||||
background_palette: u8,
|
||||
object_palette_0: u8,
|
||||
object_palette_1: u8,
|
||||
scrollx: u8,
|
||||
scrolly: u8,
|
||||
windowx: u8,
|
||||
windowy: u8,
|
||||
curline: u8,
|
||||
|
||||
vram: Box<[u8]>,
|
||||
|
||||
current_ticks: u16,
|
||||
current_mode: DisplayMode,
|
||||
// TODO
|
||||
}
|
||||
|
||||
impl Display {
|
||||
pub fn new() -> Display {
|
||||
Display::default()
|
||||
Display {
|
||||
control: 0,
|
||||
status: 0,
|
||||
background_palette: 0,
|
||||
object_palette_0: 0,
|
||||
object_palette_1: 0,
|
||||
scrollx: 0,
|
||||
scrolly: 0,
|
||||
windowx: 0,
|
||||
windowy: 0,
|
||||
curline: 0,
|
||||
|
||||
current_ticks: 0,
|
||||
current_mode: DisplayMode::default(),
|
||||
vram: vec![0; VRAM_SIZE].into_boxed_slice(),
|
||||
}
|
||||
}
|
||||
|
||||
pub fn write_byte(&mut self, addr: u16, val: u8) {
|
||||
match addr {
|
||||
0x8000 ... 0x9FFF => self.vram[(addr - 0x8000) as usize] = val,
|
||||
0xFF40 => self.control = val,
|
||||
0xFF41 => self.status = val,
|
||||
0xFF42 => self.scrolly = val,
|
||||
0xFF43 => self.scrollx = val,
|
||||
0xFF44 => self.curline = 0,
|
||||
0xFF47 => self.background_palette = val,
|
||||
0xFF48 => self.object_palette_0 = val,
|
||||
0xFF49 => self.object_palette_1 = val,
|
||||
0xFF4A => self.windowy = val,
|
||||
0xFF4B => self.windowx = val,
|
||||
_ => panic!("Display: Write {:02X} to {:04X} unsupported", val, addr),
|
||||
}
|
||||
}
|
||||
|
||||
pub fn read_byte(&self, addr: u16) -> u8 {
|
||||
match addr {
|
||||
0x8000 ... 0x9FFF => self.vram[(addr - 0x8000) as usize],
|
||||
0xFF40 => self.control,
|
||||
0xFF41 => self.status,
|
||||
0xFF42 => self.scrolly,
|
||||
0xFF43 => self.scrollx,
|
||||
0xFF44 => self.curline,
|
||||
0xFF47 => self.background_palette,
|
||||
0xFF48 => self.object_palette_0,
|
||||
0xFF49 => self.object_palette_1,
|
||||
0xFF4A => self.windowy,
|
||||
0xFF4B => self.windowx,
|
||||
_ => panic!("Display: Read from {:04X} unsupported", addr),
|
||||
}
|
||||
}
|
||||
|
||||
// Do we want to have a time delta here?
|
||||
pub fn tick(&mut self, ticks: u16) {
|
||||
self.current_ticks += ticks;
|
||||
match self.current_mode {
|
||||
DisplayMode::Scanline => {
|
||||
if self.current_ticks > TICKS_END_SCANLINE {
|
||||
self.current_ticks = 0;
|
||||
self.current_mode = DisplayMode::Readmode;
|
||||
}
|
||||
},
|
||||
DisplayMode::Readmode => {
|
||||
if self.current_ticks > TICKS_END_READMODE {
|
||||
self.current_ticks = 0;
|
||||
self.current_mode = DisplayMode::HBlank;
|
||||
}
|
||||
},
|
||||
DisplayMode::HBlank => {
|
||||
if self.current_ticks > TICKS_END_HBLANK {
|
||||
self.current_ticks = 0;
|
||||
self.curline += 1;
|
||||
if self.curline == 143 {
|
||||
self.current_mode = DisplayMode::VBlank;
|
||||
} else {
|
||||
self.current_mode = DisplayMode::Scanline;
|
||||
}
|
||||
}
|
||||
},
|
||||
DisplayMode::VBlank => {
|
||||
if self.current_ticks > TICKS_END_VBLANK {
|
||||
self.current_ticks = 0;
|
||||
self.curline += 1;
|
||||
if self.curline > 153 {
|
||||
self.current_mode = DisplayMode::Scanline;
|
||||
self.curline = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn renderscan(&mut self) {
|
||||
// TODO: Allow switching of tile map
|
||||
let tilemap: u16 = 0x1800;
|
||||
let map_offset_y: u8 = self.curline.wrapping_add(self.scrolly);
|
||||
let map_offset_x: u8 = self.scrollx;
|
||||
|
||||
let tile_index_y: u8 = map_offset_y / 8;
|
||||
|
||||
// Render line
|
||||
for render_x in 0 .. 159 {
|
||||
let tile_index_x: u8 = render_x / 8;
|
||||
let tile_offset_x: u8 = render_x % 8;
|
||||
|
||||
// TODO: Draw bit
|
||||
// let tile_base_addr = tilemap + tile_id*128
|
||||
// pixel(render_x, map_offset_y) := *tile_base_addr + 2* *(tile_base_addr+1)
|
||||
//[tile_index_x][tile_index_y]
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
pub fn vblank_interrupt(&mut self) {
|
||||
self.curline += 1;
|
||||
if self.curline > 153 {
|
||||
|
||||
@ -1,5 +1,4 @@
|
||||
const RAM_SIZE: usize = 0x2000;
|
||||
const VRAM_SIZE: usize = 0x2000;
|
||||
const HIRAM_SIZE: usize = (0xFFFE - 0xFF80) + 1;
|
||||
|
||||
const INTERRUPT_DISPLAY: u8 = 1 << 1;
|
||||
@ -7,18 +6,23 @@ const INTERRUPT_DISPLAY_VBLANK: u8 = 1 << 0;
|
||||
|
||||
use super::display;
|
||||
use super::sound;
|
||||
use super::timer;
|
||||
use super::serial;
|
||||
|
||||
pub struct Interconnect {
|
||||
bios: Box<[u8]>,
|
||||
rom: Box<[u8]>,
|
||||
ram: Box<[u8]>,
|
||||
vram: Box<[u8]>,
|
||||
hiram: Box<[u8]>,
|
||||
sound: sound::Sound,
|
||||
display: display::Display,
|
||||
interrupt: u8,
|
||||
timer: u8,
|
||||
iflags: u8,
|
||||
itimer: u8,
|
||||
disable_bootrom: u8,
|
||||
infrared_com_port: u8,
|
||||
serial: serial::Serial,
|
||||
timer: timer::Timer,
|
||||
}
|
||||
|
||||
impl Interconnect {
|
||||
@ -27,23 +31,30 @@ impl Interconnect {
|
||||
bios: bios,
|
||||
rom: rom,
|
||||
ram: vec![0; RAM_SIZE].into_boxed_slice(),
|
||||
vram: vec![0; VRAM_SIZE].into_boxed_slice(),
|
||||
hiram: vec![0; HIRAM_SIZE].into_boxed_slice(),
|
||||
sound: sound::Sound::new(),
|
||||
display: display::Display::new(),
|
||||
// Refactor those
|
||||
iflags: 0,
|
||||
interrupt: 0,
|
||||
timer: 0,
|
||||
infrared_com_port: 0,
|
||||
itimer: 0,
|
||||
disable_bootrom: 0,
|
||||
timer: timer::Timer::new(),
|
||||
serial: serial::Serial::new(),
|
||||
}
|
||||
}
|
||||
|
||||
// Somehow we need different timers for this.
|
||||
pub fn tick(&mut self) {
|
||||
self.timer += 1;
|
||||
if self.timer == 5 {
|
||||
pub fn tick(&mut self, cycles: u16) {
|
||||
/*
|
||||
self.itimer += 1;
|
||||
if self.itimer == 5 {
|
||||
self.display_blank_interrupt();
|
||||
self.timer = 0;
|
||||
self.itimer = 0;
|
||||
}
|
||||
*/
|
||||
self.display.tick(cycles * 4);
|
||||
}
|
||||
|
||||
pub fn display_blank_interrupt(&mut self) {
|
||||
@ -71,12 +82,15 @@ impl Interconnect {
|
||||
self.rom[addr as usize]
|
||||
}
|
||||
}
|
||||
0x8000 ... 0x9FFF => {
|
||||
self.vram[(addr - 0x8000) as usize]
|
||||
},
|
||||
0x8000 ... 0x9FFF => self.display.read_byte(addr),
|
||||
0xC000 ... 0xDFFF => {
|
||||
self.ram[(addr - 0xC000) as usize]
|
||||
},
|
||||
0xFF01 ... 0xFF02 => self.serial.read_byte(addr),
|
||||
0xFF04 ... 0xFF07 => self.timer.read_byte(addr),
|
||||
0xFF0F => {
|
||||
self.iflags
|
||||
},
|
||||
0xFF10 ... 0xFF26 => {
|
||||
self.sound.read_byte(addr)
|
||||
},
|
||||
@ -86,6 +100,9 @@ impl Interconnect {
|
||||
0xFF50 => {
|
||||
self.disable_bootrom
|
||||
},
|
||||
0xFF56 => {
|
||||
self.infrared_com_port
|
||||
}
|
||||
0xFF80 ... 0xFFFE => {
|
||||
self.hiram[(addr - 0xFF80) as usize]
|
||||
},
|
||||
@ -100,7 +117,6 @@ impl Interconnect {
|
||||
|
||||
pub fn write_byte(&mut self, addr: u16, val: u8) {
|
||||
// TODO: Make this more beautful
|
||||
// TODO: Write byte
|
||||
/*
|
||||
0000 7FFF Cartridge
|
||||
8000 9FFF Video RAM
|
||||
@ -115,12 +131,15 @@ impl Interconnect {
|
||||
*/
|
||||
|
||||
match addr {
|
||||
0x8000 ... 0x9FFF => {
|
||||
self.vram[(addr - 0x8000) as usize] = val;
|
||||
},
|
||||
0x8000 ... 0x9FFF => self.display.write_byte(addr, val),
|
||||
0xC000 ... 0xDFFF => {
|
||||
self.ram[(addr - 0xC000) as usize] = val;
|
||||
},
|
||||
0xFF01 ... 0xFF02 => self.serial.write_byte(addr, val),
|
||||
0xFF04 ... 0xFF07 => self.timer.write_byte(addr, val),
|
||||
0xFF0F => {
|
||||
self.iflags = val;
|
||||
}
|
||||
0xFF10 ... 0xFF26 => {
|
||||
self.sound.write_byte(addr, val);
|
||||
},
|
||||
@ -129,7 +148,10 @@ impl Interconnect {
|
||||
},
|
||||
0xFF50 => {
|
||||
self.disable_bootrom = val;
|
||||
}
|
||||
},
|
||||
0xFF56 => {
|
||||
self.infrared_com_port = val;
|
||||
},
|
||||
0xFF80 ... 0xFFFE => {
|
||||
self.hiram[(addr - 0xFF80) as usize] = val;
|
||||
},
|
||||
|
||||
@ -10,7 +10,8 @@ mod cpu;
|
||||
mod display;
|
||||
mod interconnect;
|
||||
mod sound;
|
||||
|
||||
mod timer;
|
||||
mod serial;
|
||||
|
||||
fn main() {
|
||||
let bios_path = env::args().nth(1).unwrap();
|
||||
|
||||
27
src/serial.rs
Normal file
27
src/serial.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[derive(Default, Debug)]
|
||||
pub struct Serial {
|
||||
data: u8,
|
||||
control: u8,
|
||||
}
|
||||
|
||||
impl Serial {
|
||||
pub fn new() -> Serial {
|
||||
Serial::default()
|
||||
}
|
||||
|
||||
pub fn write_byte(&mut self, addr: u16, val: u8) {
|
||||
match addr {
|
||||
0xFF01 => self.data = val,
|
||||
0xFF02 => self.control = val,
|
||||
_ => panic!("Serial: Write {:02X} to {:04X} unsupported", val, addr),
|
||||
}
|
||||
}
|
||||
|
||||
pub fn read_byte(&self, addr: u16) -> u8 {
|
||||
match addr {
|
||||
0xFF01 => self.data,
|
||||
0xFF02 => self.control,
|
||||
_ => panic!("Serial: Read from {:04X} unsupported", addr),
|
||||
}
|
||||
}
|
||||
}
|
||||
30
src/timer.rs
Normal file
30
src/timer.rs
Normal file
@ -0,0 +1,30 @@
|
||||
#[derive(Default, Debug)]
|
||||
pub struct Timer {
|
||||
tima: u8,
|
||||
tma: u8,
|
||||
tac: u8
|
||||
}
|
||||
|
||||
impl Timer {
|
||||
pub fn new() -> Timer {
|
||||
Timer::default()
|
||||
}
|
||||
|
||||
pub fn write_byte(&mut self, addr: u16, val: u8) {
|
||||
match addr {
|
||||
0xFF05 => self.tima = val,
|
||||
0xFF06 => self.tma = val,
|
||||
0xFF07 => self.tac = val,
|
||||
_ => panic!("Timer: Write {:02X} to {:04X} unsupported", val, addr),
|
||||
}
|
||||
}
|
||||
|
||||
pub fn read_byte(&self, addr: u16) -> u8 {
|
||||
match addr {
|
||||
0xFF05 => self.tima,
|
||||
0xFF06 => self.tma,
|
||||
0xFF07 => self.tac,
|
||||
_ => panic!("Timer: Read from {:04X} unsupported", addr),
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user