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Move more logic to functions

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This commit is contained in:
Kevin Hamacher 2016-05-26 20:51:23 +02:00
parent 0fdfa9ae63
commit 31117963e5
1 changed files with 75 additions and 126 deletions
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201
src/cpu.rs
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@ -229,6 +229,15 @@ impl CPU {
} }
} }
fn pop_rr(&mut self, r1: usize, r2: usize) -> u8 {
if self.debug {
println!("POP {}{}", REG_NAMES[r1], REG_NAMES[r2]);
}
let val: u16 = self.interconnect.read_word(self.sp);
self.sp += 2;
self.set_pair_value(r1, r2, val);
12
}
fn push_rr(&mut self, r1: usize, r2: usize) -> u8 { fn push_rr(&mut self, r1: usize, r2: usize) -> u8 {
if self.debug { if self.debug {
println!("PUSH {}{}", REG_NAMES[r1], REG_NAMES[r2]); println!("PUSH {}{}", REG_NAMES[r1], REG_NAMES[r2]);
@ -238,6 +247,16 @@ impl CPU {
16 16
} }
fn inc_rr(&mut self, r1: usize, r2: usize) -> u8 {
if self.debug {
println!("INC {}{}", REG_NAMES[r1], REG_NAMES[r2]);
}
let v = self.get_pair_value(r1, r2);
let v = v.wrapping_add(1);
self.set_pair_value(r1, r2, v);
8
}
fn push(&mut self, val: u16) { fn push(&mut self, val: u16) {
self.interconnect.write_word(self.sp - 2, val); self.interconnect.write_word(self.sp - 2, val);
self.sp -= 2; self.sp -= 2;
@ -256,12 +275,35 @@ impl CPU {
} }
} }
fn ld_r_v(&mut self, r: usize) -> u8 {
let val: u8 = self.load_args(1)[0];
if self.debug {
println!("LD {}, {:02X}", REG_NAMES[r], val);
}
self.set_8bit_reg(r, val);
if r == REG_N_HL {
12
} else {
8
}
}
fn ld_rr_vv(&mut self, r1: usize, r2: usize) -> u8 {
let val: u16 = to_u16(self.load_args(2));
if self.debug {
println!("LD {}{}, {:04X}", REG_NAMES[r1], REG_NAMES[r2], val);
}
self.set_pair_value(r1, r2, val);
12
}
fn reg_inc(&mut self, reg_id: usize) -> u8 { fn reg_inc(&mut self, reg_id: usize) -> u8 {
if self.debug { if self.debug {
println!("INC {}", REG_NAMES[reg_id]); println!("INC {}", REG_NAMES[reg_id]);
} }
self.regs[reg_id] = self.regs[reg_id].wrapping_add(1); let val = self.get_8bit_reg(reg_id).wrapping_add(1);
if self.regs[reg_id] == 0 { self.set_8bit_reg(reg_id, val);
if val == 0 {
self.flags |= FLAG_Z; self.flags |= FLAG_Z;
} }
self.flags &= !FLAG_N; self.flags &= !FLAG_N;
@ -272,8 +314,9 @@ impl CPU {
if self.debug { if self.debug {
println!("DEC {}", REG_NAMES[reg_id]); println!("DEC {}", REG_NAMES[reg_id]);
} }
self.regs[reg_id] = self.regs[reg_id].wrapping_sub(1); let val = self.get_8bit_reg(reg_id).wrapping_sub(1);
if self.regs[reg_id] == 0 { self.set_8bit_reg(reg_id, val);
if val == 0 {
self.flags |= FLAG_Z; self.flags |= FLAG_Z;
} else { } else {
self.flags &= !FLAG_Z; self.flags &= !FLAG_Z;
@ -316,15 +359,7 @@ impl CPU {
} }
4 4
}, },
0x01 => { 0x01 => self.ld_rr_vv(REG_N_B, REG_N_C),
if self.debug {
println!("LD (BC), A");
}
let addr: u16 = self.get_pair_value(REG_B, REG_C);
let val: u8 = self.regs[REG_A];
self.interconnect.write_byte(addr, val);
12
},
0x02 => { 0x02 => {
if self.debug { if self.debug {
println!("LD (BC),A"); println!("LD (BC),A");
@ -334,35 +369,13 @@ impl CPU {
self.interconnect.write_byte(addr, val); self.interconnect.write_byte(addr, val);
8 8
}, },
0x04 => self.reg_inc(REG_B), 0x04 => self.reg_inc(REG_N_B),
0x05 => self.reg_dec(REG_B), 0x05 => self.reg_dec(REG_N_B),
0x06 => { 0x06 => self.ld_r_v(REG_N_B),
let args = self.load_args(1); 0x0C => self.reg_inc(REG_N_C),
if self.debug { 0x0D => self.reg_dec(REG_N_C),
println!("LD B, {:02x}", args[0]); 0x0E => self.ld_r_v(REG_N_C),
} 0x11 => self.ld_rr_vv(REG_N_D, REG_N_E),
self.regs[REG_B] = args[0];
8
},
0x0C => self.reg_inc(REG_C),
0x0D => self.reg_dec(REG_C),
0x0E => {
let args = self.load_args(1);
if self.debug {
println!("LD C, {:02x}", args[0]);
}
self.regs[REG_C] = args[0];
8
},
0x11 => {
let args = self.load_args(2);
let val = to_u16(args);
if self.debug {
println!("LD DE, {:04x}", val);
}
self.set_pair_value(REG_D, REG_E, val);
12
},
0x12 => { 0x12 => {
if self.debug { if self.debug {
println!("LD (DE),A"); println!("LD (DE),A");
@ -372,24 +385,10 @@ impl CPU {
self.interconnect.write_byte(addr, val); self.interconnect.write_byte(addr, val);
12 12
}, },
0x13 => { 0x13 => self.inc_rr(REG_D, REG_E),
if self.debug { 0x14 => self.reg_inc(REG_N_D),
println!("INC DE"); 0x15 => self.reg_dec(REG_N_D),
} 0x16 => self.ld_r_v(REG_N_D),
let old_value = self.get_pair_value(REG_D, REG_E);
self.set_pair_value(REG_D, REG_E, old_value + 1);
8
},
0x14 => self.reg_inc(REG_D),
0x15 => self.reg_dec(REG_D),
0x16 => {
let args = self.load_args(1);
if self.debug {
println!("LD D, {:02x}", args[0]);
}
self.regs[REG_D] = args[0];
8
},
0x17 => { 0x17 => {
if self.debug { if self.debug {
println!("RLA"); println!("RLA");
@ -429,16 +428,9 @@ impl CPU {
self.regs[REG_A] = self.interconnect.read_byte(self.get_pair_value(REG_D, REG_E)); self.regs[REG_A] = self.interconnect.read_byte(self.get_pair_value(REG_D, REG_E));
8 8
}, },
0x1C => self.reg_inc(REG_E), 0x1C => self.reg_inc(REG_N_E),
0x1D => self.reg_dec(REG_E), 0x1D => self.reg_dec(REG_N_E),
0x1E => { 0x1E => self.ld_r_v(REG_N_E),
let args = self.load_args(1);
if self.debug {
println!("LD E, {:02x}", args[0]);
}
self.regs[REG_E] = args[0];
8
},
0x20 => { 0x20 => {
let args = self.load_args(1); let args = self.load_args(1);
if self.debug { if self.debug {
@ -456,14 +448,7 @@ impl CPU {
8 8
} }
} }
0x21 => { 0x21 => self.ld_rr_vv(REG_N_H, REG_N_L),
let value = to_u16(self.load_args(2));
if self.debug {
println!("LD HL, {:04x}", value);
}
self.set_pair_value(REG_H, REG_L, value);
12
},
0x22 => { 0x22 => {
if self.debug { if self.debug {
println!("LD (HL+), A"); println!("LD (HL+), A");
@ -473,24 +458,10 @@ impl CPU {
self.set_pair_value(REG_H, REG_L, addr + 1); self.set_pair_value(REG_H, REG_L, addr + 1);
8 8
}, },
0x23 => { 0x23 => self.inc_rr(REG_H, REG_L),
if self.debug { 0x24 => self.reg_inc(REG_N_H),
println!("INC HL"); 0x25 => self.reg_dec(REG_N_H),
} 0x26 => self.ld_r_v(REG_N_H),
let old_value = self.get_pair_value(REG_H, REG_L);
self.set_pair_value(REG_H, REG_L, old_value + 1);
8
},
0x24 => self.reg_inc(REG_H),
0x25 => self.reg_dec(REG_H),
0x26 => {
let args = self.load_args(1);
if self.debug {
println!("LD H, {:02x}", args[0]);
}
self.regs[REG_H] = args[0];
8
},
0x28 => { 0x28 => {
let args = self.load_args(1); let args = self.load_args(1);
let target; let target;
@ -517,21 +488,14 @@ impl CPU {
self.regs[REG_A] = self.interconnect.read_byte(addr); self.regs[REG_A] = self.interconnect.read_byte(addr);
8 8
}, },
0x2C => self.reg_inc(REG_L), 0x2C => self.reg_inc(REG_N_L),
0x2D => self.reg_dec(REG_L), 0x2D => self.reg_dec(REG_N_L),
0x2E => { 0x2E => self.ld_r_v(REG_N_L),
let args = self.load_args(1);
if self.debug {
println!("LD L, {:02x}", args[0]);
}
self.regs[REG_L] = args[0];
8
},
0x31 => { 0x31 => {
let args = self.load_args(2); let args = self.load_args(2);
self.sp = to_u16(args); self.sp = to_u16(args);
if self.debug { if self.debug {
println!("LD SP, {:02x}", self.sp); println!("LD SP, {:04x}", self.sp);
} }
12 12
}, },
@ -555,16 +519,9 @@ impl CPU {
self.interconnect.write_byte(addr, args[0]); self.interconnect.write_byte(addr, args[0]);
12 12
}, },
0x3C => self.reg_inc(REG_A), 0x3C => self.reg_inc(REG_N_A),
0x3D => self.reg_dec(REG_A), 0x3D => self.reg_dec(REG_N_A),
0x3E => { 0x3E => self.ld_r_v(REG_N_A),
let args = self.load_args(1);
if self.debug {
println!("LD A, {:02x}", args[0]);
}
self.regs[REG_A] = args[0];
8
},
// LDs // LDs
0x40 ... 0x47 => self.ld_r_r(REG_N_B, (instruction - 0x40) as usize), 0x40 ... 0x47 => self.ld_r_r(REG_N_B, (instruction - 0x40) as usize),
@ -677,15 +634,7 @@ impl CPU {
} }
4 4
}, },
0xC1 => { 0xC1 => self.pop_rr(REG_B, REG_C),
if self.debug {
println!("POP BC");
}
let val: u16 = self.interconnect.read_word(self.sp);
self.sp += 2;
self.set_pair_value(REG_B, REG_C, val);
12
},
0xC2 => { 0xC2 => {
let addr: u16 = to_u16(self.load_args(2)); let addr: u16 = to_u16(self.load_args(2));
if self.debug { if self.debug {