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even more complains

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This commit is contained in:
Kevin Hamacher 2020-02-20 20:18:54 +01:00
parent f07a0032eb
commit 2fb40e7b10
1 changed files with 13 additions and 35 deletions
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48
src/cpu.rs
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@ -141,12 +141,7 @@ impl CPU {
fn adc_r(&mut self, val: u8) {
let old: u8 = self.regs[REG_A];
let mut new: u8 = old;
let c: u8;
if self.flags & FLAG_C == FLAG_C {
c = 1;
} else {
c = 0;
}
let c = if self.flags & FLAG_C == FLAG_C { 1 } else { 0 };
new = new.wrapping_add(val);
new = new.wrapping_add(c);
self.regs[REG_A] = new;
@ -172,12 +167,7 @@ impl CPU {
fn sbc_r(&mut self, val: u8) {
let old: u8 = self.regs[REG_A];
let mut new: u8 = old as u8;
let c: u8;
if self.flags & FLAG_C == FLAG_C {
c = 1;
} else {
c = 0;
}
let c = if self.flags & FLAG_C == FLAG_C { 1 } else { 0 };
new = new.wrapping_sub(val);
new = new.wrapping_sub(c);
@ -227,12 +217,11 @@ impl CPU {
println!("RLC {}", REG_NAMES[reg_id]);
}
let nval: u8;
if val & 0x80 == 0x80 {
nval = val << 1 | 1;
let nval = if val & 0x80 == 0x80 {
val << 1 | 1
} else {
nval = val << 1;
}
val << 1
};
self.set_8bit_reg(reg_id, nval);
self.set_clear_flag(FLAG_C, val & 0x80 == 0x80);
@ -266,12 +255,7 @@ impl CPU {
}
let carry = self.flags & FLAG_C > 0;
let nval: u8;
if !carry {
nval = val << 1;
} else {
nval = val << 1 | 1;
}
let nval = if !carry { val << 1 } else { val << 1 | 1 };
self.set_8bit_reg(reg_id, nval);
self.set_clear_flag(FLAG_C, val & 0x80 == 0x80);
self.set_clear_flag(FLAG_Z, nval == 0);
@ -287,12 +271,7 @@ impl CPU {
}
let carry = self.flags & FLAG_C > 0;
let v: u8;
if !carry {
v = val >> 1;
} else {
v = (val >> 1) | 0x80;
}
let v = if !carry { val >> 1 } else { (val >> 1) | 0x80 };
self.set_8bit_reg(reg_id, v);
self.set_clear_flag(FLAG_C, val & 1 == 1);
self.set_clear_flag(FLAG_Z, v == 0);
@ -788,7 +767,7 @@ impl CPU {
self.clear_flag(FLAG_N);
// Some magic formula
self.set_clear_flag(FLAG_C, val1 as usize + val2 as usize & 0x10000 == 0x10000);
self.set_clear_flag(FLAG_C, (val1 as usize + val2 as usize) & 0x10000 == 0x10000);
self.set_clear_flag(FLAG_H, (val1 ^ val2 ^ res) & 0x1000 == 0x1000);
8
}
@ -1579,12 +1558,11 @@ impl CPU {
if self.debug {
println!("ADD SP, {:02X}", arg);
}
let t: u16;
if arg > 0 {
t = self.sp.wrapping_add(arg as u16);
let t = if arg > 0 {
self.sp.wrapping_add(arg as u16)
} else {
t = self.sp.wrapping_sub((-arg) as u16);
}
self.sp.wrapping_sub((-arg) as u16)
};
let sp = self.sp;
self.clear_flag(FLAG_N);
self.clear_flag(FLAG_Z);