From 2b2659986e399e397a5fb15d4a6bb9723c79b961 Mon Sep 17 00:00:00 2001 From: Kevin Hamacher Date: Sun, 29 May 2016 20:53:17 +0200 Subject: [PATCH] Fix a couple CB opcodes; Pass more tests. --- Readme.md | 6 +++--- src/cartridge.rs | 4 ++-- src/cpu.rs | 56 +++++++++++++++++++++++++++++++----------------- 3 files changed, 41 insertions(+), 25 deletions(-) diff --git a/Readme.md b/Readme.md index 5816f5b..aa012c1 100644 --- a/Readme.md +++ b/Readme.md @@ -13,10 +13,10 @@ Display is able to render tiles + sprites, 8x16 sprites are implemented but unte - Test 02 fails because interrupts are not fully implemented. - Test 03 passes - Test 04 passes - - Test 05 fails - - Test 06 passes (LD R, R) + - Test 05 passes + - Test 06 passes - Test 07 fails - Test 08 fails - - Test 09 fails + - Test 09 passes - Test 10 passes - Test 11 fails diff --git a/src/cartridge.rs b/src/cartridge.rs index edfb9f8..a8a0ccb 100644 --- a/src/cartridge.rs +++ b/src/cartridge.rs @@ -91,7 +91,7 @@ impl Cartridge { 0x0000 ... 0x3FFF => self.rom[addr as usize], 0x4000 ... 0x7FFF => { let addr = addr - 0x4000; - println!("BankNo: {:02X}", self.bank_no); + // println!("BankNo: {:02X}", self.bank_no); let abs_addr: usize = addr as usize + self.bank_no as usize * 0x4000; let val: u8 = self.rom[abs_addr]; val @@ -121,7 +121,7 @@ impl Cartridge { if self.bank_mode == 0 { bank |= self.bank_no_high << 5; } - println!("BankNo: {:02X}", bank); + // println!("BankNo: {:02X}", bank); let abs_addr: usize = addr as usize + bank as usize * 0x4000; let val: u8 = self.rom[abs_addr]; val diff --git a/src/cpu.rs b/src/cpu.rs index b5fd4f3..1c67508 100644 --- a/src/cpu.rs +++ b/src/cpu.rs @@ -200,14 +200,16 @@ impl CPU { println!("RLC {}", REG_NAMES[reg_id]); } - self.set_clear_flag(FLAG_C, val & 0x80 == 80); + let nval: u8; if val & 0x80 == 0x80 { - self.set_8bit_reg(reg_id, val << 1 | 1); + nval = val << 1 | 1; } else { - self.set_8bit_reg(reg_id, val << 1); + nval = val << 1; } + self.set_8bit_reg(reg_id, nval); - self.set_clear_flag(FLAG_Z, val == 0); + self.set_clear_flag(FLAG_C, val & 0x80 == 0x80); + self.set_clear_flag(FLAG_Z, nval == 0); self.clear_flag(FLAG_N); self.clear_flag(FLAG_H); }, @@ -237,13 +239,15 @@ impl CPU { } let carry = self.flags & FLAG_C > 0; - self.set_clear_flag(FLAG_C, val & 0x80 == 0x80); + let nval: u8; if !carry { - self.set_8bit_reg(reg_id, val << 1); + nval = val << 1; } else { - self.set_8bit_reg(reg_id, val << 1 | 1); + nval = val << 1 | 1; } - self.clear_flag(FLAG_Z); + self.set_8bit_reg(reg_id, nval); + self.set_clear_flag(FLAG_C, val & 0x80 == 0x80); + self.set_clear_flag(FLAG_Z, nval == 0); self.clear_flag(FLAG_N); self.clear_flag(FLAG_H); }, @@ -255,13 +259,15 @@ impl CPU { } let carry = self.flags & FLAG_C > 0; - self.set_clear_flag(FLAG_C, val & 1 == 1); + let v: u8; if !carry { - self.set_8bit_reg(reg_id, val >> 1); + v = val >> 1; } else { - self.set_8bit_reg(reg_id, val >> 1 | 0x80); + v = (val >> 1) | 0x80; } - self.clear_flag(FLAG_Z); + self.set_8bit_reg(reg_id, v); + self.set_clear_flag(FLAG_C, val & 1 == 1); + self.set_clear_flag(FLAG_Z, v == 0); self.clear_flag(FLAG_N); self.clear_flag(FLAG_H); }, @@ -271,7 +277,9 @@ impl CPU { println!("SLA {}", REG_NAMES[reg_id]); } let v: u8 = self.get_8bit_reg(reg_id); - self.set_clear_flag(FLAG_C, v & 0x80 > 0); + self.flags = 0; + self.set_clear_flag(FLAG_C, v & 0x80 == 0x80); + self.set_clear_flag(FLAG_Z, v & 0x7F == 0); self.set_8bit_reg(reg_id, v << 1); }, 0x28 ... 0x2F => { @@ -280,8 +288,11 @@ impl CPU { println!("SRA {}", REG_NAMES[reg_id]); } let v: u8 = self.get_8bit_reg(reg_id); - self.set_clear_flag(FLAG_C, v & 1 > 0); - self.set_8bit_reg(reg_id, v >> 1 | v & 0x80); + let nv = (v >> 1) | (v & 0x80); + self.set_8bit_reg(reg_id, nv); + self.flags = 0; + self.set_clear_flag(FLAG_Z, nv == 0); + self.set_clear_flag(FLAG_C, v & 1 == 1); }, 0x30 ... 0x37 => { let reg_id = (instruction - 0x30) as usize; @@ -289,7 +300,9 @@ impl CPU { println!("SWAP {}", REG_NAMES[reg_id]); } let v: u8 = self.get_8bit_reg(reg_id); - self.set_8bit_reg(reg_id, v << 4 | v >> 4); + self.set_8bit_reg(reg_id, (v << 4) | (v >> 4)); + self.flags = 0; + self.set_clear_flag(FLAG_Z, v == 0); }, 0x38 ... 0x3F => { let reg_id = (instruction - 0x38) as usize; @@ -750,10 +763,11 @@ impl CPU { if self.debug { println!("INC {}", REG_NAMES[reg_id]); } - let val = self.get_8bit_reg(reg_id).wrapping_add(1); + let old = self.get_8bit_reg(reg_id); + let val = old.wrapping_add(1); self.set_8bit_reg(reg_id, val); self.set_clear_flag(FLAG_Z, val == 0); - // self.set_clear_flag(FLAG_C, val == 0); + self.set_clear_flag(FLAG_H, (old & 0xF) + 1 > 0xF); self.clear_flag(FLAG_N); 4 } @@ -783,11 +797,13 @@ impl CPU { if self.debug { println!("DEC {}", REG_NAMES[reg_id]); } - let val = self.get_8bit_reg(reg_id).wrapping_sub(1); + let old = self.get_8bit_reg(reg_id); + let val = old.wrapping_sub(1); self.set_8bit_reg(reg_id, val); self.set_clear_flag(FLAG_Z, val == 0); // self.set_clear_flag(FLAG_C, val == 255); + self.set_clear_flag(FLAG_H, old & 0x0F == 0); self.set_flag(FLAG_N); 4 } @@ -1198,6 +1214,7 @@ impl CPU { } self.flags ^= FLAG_C; self.clear_flag(FLAG_N); + self.clear_flag(FLAG_H); 4 } @@ -1365,7 +1382,6 @@ impl CPU { self.jmp_p_condition("Z".to_owned(), c) } 0xCB => { - // Prefix CB. This is annoying. self.run_prefix_instruction(); 12 // TODO: Verify that this is the case for all prefix instructions. },