From dc7d3d62682d23df0509d5f679709d62d937d5f8 Mon Sep 17 00:00:00 2001 From: Kevin Hamacher Date: Mon, 28 Nov 2022 19:52:23 +0100 Subject: [PATCH] Format + some clipy --- src/chip.rs | 16 ++++------------ src/cpu.rs | 36 +++++++++++++++--------------------- src/devices/mod.rs | 4 ++-- src/devices/usart.rs | 1 - src/gdbstub.rs | 2 +- src/regs.rs | 4 ++-- 6 files changed, 24 insertions(+), 39 deletions(-) diff --git a/src/chip.rs b/src/chip.rs index 51373d6..f9d702e 100644 --- a/src/chip.rs +++ b/src/chip.rs @@ -20,18 +20,10 @@ impl Chip { let mut dev_tree = DeviceTree::new(log.clone()); // Add RAM and USART - dev_tree.add_device(Device::new(Box::new(ram_device), 0x2000, 0x2000)); - dev_tree.add_device(Device::new(Box::new(internal_regs), 0, 0x40)); - dev_tree.add_device(Device::new( - Box::new(usart_device), - 0x8A0, - 0x8A7 - 0x8A0 + 1, - )); - dev_tree.add_device(Device::new( - Box::new(Oscillator::new(log.clone())), - 0x50, - 0x07, - )); + dev_tree.add_device(Device::new(ram_device, 0x2000, 0x2000)); + dev_tree.add_device(Device::new(internal_regs, 0, 0x40)); + dev_tree.add_device(Device::new(usart_device, 0x8A0, 0x8A7 - 0x8A0 + 1)); + dev_tree.add_device(Device::new(Oscillator::new(log.clone()), 0x50, 0x07)); Self { log: log.clone(), diff --git a/src/cpu.rs b/src/cpu.rs index a41b9d2..d91b8c1 100644 --- a/src/cpu.rs +++ b/src/cpu.rs @@ -1,12 +1,10 @@ #![allow(dead_code)] #![allow(unused_variables)] -use chip_definitions; -use decoder; -use decoder::{IncrementMode, Instruction}; -use regs::{GeneralPurposeRegister, GeneralPurposeRegisterPair, StatusFlag}; - +use chip_definitions::IOAdress; +use decoder::{self, IncrementMode, Instruction}; use devices::DeviceTree; +use regs::{GeneralPurposeRegister, GeneralPurposeRegisterPair, StatusFlag}; use std::fmt; @@ -76,14 +74,14 @@ impl CPU { } pub fn get_sp(&self, mem: &mut DeviceTree) -> u16 { - let spl: u16 = mem.read(chip_definitions::IOAdress::SPL as u32) as u16; - let sph: u16 = mem.read(chip_definitions::IOAdress::SPH as u32) as u16; + let spl: u16 = mem.read(IOAdress::SPL as u32) as u16; + let sph: u16 = mem.read(IOAdress::SPH as u32) as u16; sph << 8 | spl } fn set_sp(&self, mem: &mut DeviceTree, val: u16) { - mem.write(chip_definitions::IOAdress::SPL as u32, val as u8); - mem.write(chip_definitions::IOAdress::SPH as u32, (val >> 8) as u8); + mem.write(IOAdress::SPL as u32, val as u8); + mem.write(IOAdress::SPH as u32, (val >> 8) as u8); } fn test_flag(&self, flag: StatusFlag) -> bool { @@ -325,11 +323,11 @@ impl CPU { let base = self.get_register_pair(ptr); /* // TODO: RAMPX/Y/Z - if ptr.low() == 26 && ram[chip_definitions::IOAdress::RAMPX as usize] > 0 { + if ptr.low() == 26 && ram[IOAdress::RAMPX as usize] > 0 { panic!("Unexpected"); - } else if ptr.low() == 28 && ram[chip_definitions::IOAdress::RAMPY as usize] > 0 { + } else if ptr.low() == 28 && ram[IOAdress::RAMPY as usize] > 0 { panic!("Unexpected"); - } else if ptr.low() == 30 && ram[chip_definitions::IOAdress::RAMPZ as usize] > 0 { + } else if ptr.low() == 30 && ram[IOAdress::RAMPZ as usize] > 0 { panic!("Unexpected"); } */ @@ -351,16 +349,12 @@ impl CPU { Instruction::ELPM(ref dst_reg, ref inc_mode) => { let Zb = self.get_register_pair(&30u8.into()); // TODO: Only use required bits, other read as zero (according to datasheet) - let Z = Zb as usize - | (device_tree.read(chip_definitions::IOAdress::RAMPZ as u32) as usize) << 16; + let Z = Zb as usize | (device_tree.read(IOAdress::RAMPZ as u32) as usize) << 16; match *inc_mode { IncrementMode::PostIncrement => { self.set_register_pair(&30u8.into(), Zb.wrapping_add(1)); - device_tree.write( - chip_definitions::IOAdress::RAMPZ as u32, - (Z.wrapping_add(1) >> 16) as u8, - ); + device_tree.write(IOAdress::RAMPZ as u32, (Z.wrapping_add(1) >> 16) as u8); } _ => { // This instruction does only support None + PostIncrement @@ -553,7 +547,7 @@ impl CPU { self.update_flags_zns_8(res); } Instruction::STS16(ref addr, ref r) => { - let rampd = device_tree.read(chip_definitions::IOAdress::RAMPD as u32); + let rampd = device_tree.read(IOAdress::RAMPD as u32); if rampd != 0 { panic!("This is unexpected (for now)"); } @@ -563,7 +557,7 @@ impl CPU { self.ram_write(device_tree, *addr as u16, self.get_register(r))?; } Instruction::LDS16(ref r, ref addr) => { - let rampd = device_tree.read(chip_definitions::IOAdress::RAMPD as u32); + let rampd = device_tree.read(IOAdress::RAMPD as u32); if rampd != 0 { panic!("This is unexpected (for now)"); } @@ -667,7 +661,7 @@ impl CPU { if self.test_flag(StatusFlag::BitCopyStorage) { rv |= 1 << *v; } - let r = self.set_register(r, rv); + self.set_register(r, rv); } Instruction::SWAP(ref r) => { let rv = self.get_register(r); diff --git a/src/devices/mod.rs b/src/devices/mod.rs index 48f0554..a5b62ae 100644 --- a/src/devices/mod.rs +++ b/src/devices/mod.rs @@ -20,11 +20,11 @@ pub struct Device { } impl Device { - pub fn new(device: Box, start_addr: u32, addr_len: u32) -> Self { + pub fn new(device: T, start_addr: u32, addr_len: u32) -> Self { Self { start_addr, addr_len, - device, + device: Box::new(device), } } diff --git a/src/devices/usart.rs b/src/devices/usart.rs index b492521..55da583 100644 --- a/src/devices/usart.rs +++ b/src/devices/usart.rs @@ -110,4 +110,3 @@ impl DeviceImpl for Usart { } } } - diff --git a/src/gdbstub.rs b/src/gdbstub.rs index 89a1fac..58de710 100644 --- a/src/gdbstub.rs +++ b/src/gdbstub.rs @@ -262,7 +262,7 @@ impl<'a> GDBStub<'a> { "s" | "c" => { // Step / Continue // Parse resume from. - let resume_from = u32::from_str_radix(&*payload, 16); + let resume_from = u32::from_str_radix(&payload, 16); if let Ok(pc) = resume_from { self.chip.cpu.pc = pc; } diff --git a/src/regs.rs b/src/regs.rs index b41f479..6a7f893 100644 --- a/src/regs.rs +++ b/src/regs.rs @@ -98,7 +98,7 @@ impl From for GeneralPurposeRegister { if v > 31 { unreachable!(); } - Self { 0: v } + Self(v) } } @@ -141,7 +141,7 @@ impl From for GeneralPurposeRegisterPair { println!("v={}", v); unreachable!(); } - Self { 0: v } + Self(v) } }