From c084d4564ff2adea7e02f4450030538eb6067abb Mon Sep 17 00:00:00 2001 From: Kevin Hamacher Date: Sun, 11 Feb 2018 14:37:57 +0100 Subject: [PATCH] . --- src/cpu.rs | 2 ++ src/decoder.rs | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cpu.rs b/src/cpu.rs index bcb21c3..e59e461 100644 --- a/src/cpu.rs +++ b/src/cpu.rs @@ -459,12 +459,14 @@ impl CPU { self.set_register(r, v); self.set_clear_flag(StatusFlag::Carry, v == 0xFF); self.set_clear_flag(StatusFlag::Zero, v == 0); + self.set_clear_flag(StatusFlag::Negative, v & 0x80 == 0x80); }, Instruction::INC(ref r) => { let v = self.get_register(r).wrapping_add(1); self.set_register(r, v); self.set_clear_flag(StatusFlag::Carry, v == 0); self.set_clear_flag(StatusFlag::Zero, v == 0); + self.set_clear_flag(StatusFlag::Negative, v & 0x80 == 0x80); }, Instruction::STS16(ref addr, ref r) => { self.ram_write(ram, *addr, self.get_register(r))?; diff --git a/src/decoder.rs b/src/decoder.rs index a7f53fc..0b17eba 100644 --- a/src/decoder.rs +++ b/src/decoder.rs @@ -305,7 +305,7 @@ pub fn decode(data: &[u8]) -> Result { 0b0000_0001_0000_0000 => return Ok(Instruction::MOVW((d * 2).into(), (r * 2).into())), 0b0000_0010_0000_0000 => return Ok(Instruction::MULS((d + 16).into(), (r + 16).into())), 0b1001_0111_0000_0000 => return Ok(Instruction::SBIW(((d & 0b11) * 2 + 24).into(), K as u16)), - 0b1110_1111_0000_0000 => return Ok(Instruction::SER((d + 16).into())), + 0b1110_1111_0000_0000 => if r == 0b1111 { return Ok(Instruction::SER((d + 16).into())) } 0b1001_1010_0000_0000 => return Ok(Instruction::SBI(A, b)), 0b1001_1011_0000_0000 => return Ok(Instruction::SBIS(A, b)), 0b1001_1001_0000_0000 => return Ok(Instruction::SBIC(A, b)),