A couple more instructions, we read from UART
This commit is contained in:
parent
7136fab6af
commit
a4c521afdf
22
src/cpu.rs
22
src/cpu.rs
@ -124,7 +124,6 @@ impl CPU {
|
|||||||
} else {
|
} else {
|
||||||
// TODO: Hooks
|
// TODO: Hooks
|
||||||
if addr == chip_definitions::USARTC0_DATA {
|
if addr == chip_definitions::USARTC0_DATA {
|
||||||
// panic!("Tring to write {} via USART!", val);
|
|
||||||
print!("UART_OUT:{: <3} ({}) ", val, (val as char).escape_debug());
|
print!("UART_OUT:{: <3} ({}) ", val, (val as char).escape_debug());
|
||||||
}
|
}
|
||||||
ram[addr as usize] = val;
|
ram[addr as usize] = val;
|
||||||
@ -143,11 +142,15 @@ impl CPU {
|
|||||||
return Err(CPUError::Exit);
|
return Err(CPUError::Exit);
|
||||||
} else if addr == chip_definitions::USARTC0_STATUS {
|
} else if addr == chip_definitions::USARTC0_STATUS {
|
||||||
print!("Trying to read USART flags!");
|
print!("Trying to read USART flags!");
|
||||||
// return Err(CPUError::Exit);
|
if self.pc == 0x5AC {
|
||||||
return Ok(0x20); // Hack :D
|
// USART data check -> Yes, there is indeed data available!
|
||||||
|
return Ok(0x80);
|
||||||
|
} else {
|
||||||
|
return Ok(0x20); // Usart is ready to send.
|
||||||
|
}
|
||||||
} else if addr == chip_definitions::OSC_STATUS {
|
} else if addr == chip_definitions::OSC_STATUS {
|
||||||
// HACK: Osci is set right..
|
// HACK: Osci is set right..
|
||||||
return Ok(2);
|
return Ok(0x02);
|
||||||
}
|
}
|
||||||
Ok(ram[addr as usize])
|
Ok(ram[addr as usize])
|
||||||
}
|
}
|
||||||
@ -401,6 +404,8 @@ impl CPU {
|
|||||||
let t = self.get_register(r);
|
let t = self.get_register(r);
|
||||||
self.set_clear_flag(StatusFlag::Zero, t == 0);
|
self.set_clear_flag(StatusFlag::Zero, t == 0);
|
||||||
self.set_clear_flag(StatusFlag::Negative, t & 0x80 == 0x80);
|
self.set_clear_flag(StatusFlag::Negative, t & 0x80 == 0x80);
|
||||||
|
self.set_clear_flag(StatusFlag::SignBit, t & 0x80 == 0x80);
|
||||||
|
self.clear_flag(StatusFlag::TwosComplementOverflow);
|
||||||
},
|
},
|
||||||
Instruction::ANDI(ref d, ref v) => {
|
Instruction::ANDI(ref d, ref v) => {
|
||||||
let t = self.get_register(d) & *v;
|
let t = self.get_register(d) & *v;
|
||||||
@ -519,6 +524,11 @@ impl CPU {
|
|||||||
self.pc += 1;
|
self.pc += 1;
|
||||||
}
|
}
|
||||||
},
|
},
|
||||||
|
Instruction::COM(ref r) => {
|
||||||
|
// Rd ← $FF - Rd
|
||||||
|
let rv = 0xFFu8.wrapping_sub(self.get_register(r));
|
||||||
|
self.set_register(r, rv);
|
||||||
|
},
|
||||||
Instruction::MUL(ref r, ref d) => {
|
Instruction::MUL(ref r, ref d) => {
|
||||||
// R1:R0 ← Rd × Rr(unsigned ← unsigned × unsigned)
|
// R1:R0 ← Rd × Rr(unsigned ← unsigned × unsigned)
|
||||||
let r = self.get_register(r) as u16;
|
let r = self.get_register(r) as u16;
|
||||||
@ -529,6 +539,10 @@ impl CPU {
|
|||||||
self.set_clear_flag(StatusFlag::Carry, v & 0x80 == 0x80);
|
self.set_clear_flag(StatusFlag::Carry, v & 0x80 == 0x80);
|
||||||
self.set_clear_flag(StatusFlag::Zero, v == 0);
|
self.set_clear_flag(StatusFlag::Zero, v == 0);
|
||||||
},
|
},
|
||||||
|
Instruction::BST(ref r, ref v) => {
|
||||||
|
let r = self.get_register(r);
|
||||||
|
self.set_clear_flag(StatusFlag::BitCopyStorage, r & (1 << *v) != 0);
|
||||||
|
},
|
||||||
Instruction::NOP => {},
|
Instruction::NOP => {},
|
||||||
_ => return Err(CPUError::UnimplementedInstruction)
|
_ => return Err(CPUError::UnimplementedInstruction)
|
||||||
}
|
}
|
||||||
|
|||||||
@ -30,7 +30,7 @@ fn main() {
|
|||||||
rom[0x1d58 + 3] = 0x00;
|
rom[0x1d58 + 3] = 0x00;
|
||||||
*/
|
*/
|
||||||
|
|
||||||
for _ in 0..280000 {
|
for _ in 0..2800000 {
|
||||||
let r = cpu.step(&mut rom, &mut ram);
|
let r = cpu.step(&mut rom, &mut ram);
|
||||||
print!("[r28={:02X} r29={:02X}] ", cpu.registers[28], cpu.registers[29]);
|
print!("[r28={:02X} r29={:02X}] ", cpu.registers[28], cpu.registers[29]);
|
||||||
println!("{:?}", r);
|
println!("{:?}", r);
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user