diff --git a/src/cpu.rs b/src/cpu.rs
index ca4b92e..a62b9cc 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -53,7 +53,7 @@ impl fmt::Display for CPU {
         for i in 0..32 {
             write!(f, " R{:-2} = 0x{:02X}  ", i, self.registers[i])?;
             if (i + 1) % 10 == 0{
-                write!(f, "\n");
+                write!(f, "\n")?;
             }
         }
         write!(f, "\n")
@@ -124,7 +124,8 @@ impl CPU {
         } else {
             // TODO: Hooks
             if addr == chip_definitions::USARTC0_DATA {
-                panic!("Tring to write {} via USART!", val);
+                // panic!("Tring to write {} via USART!", val);
+                print!("UART_OUT:{: <3} ({}) ", val, (val as char).escape_debug());
             }
             ram[addr as usize] = val;
             Ok(())
@@ -138,9 +139,12 @@ impl CPU {
         } else {
             // TODO: Hooks
             if addr == chip_definitions::USARTC0_DATA {
-                panic!("Tring to read from USART!");
+                print!("Tring to read from USART!");
+                return Err(CPUError::Exit);
             } else if addr == chip_definitions::USARTC0_STATUS {
-                panic!("Trying to read USART flags!");
+                print!("Trying to read USART flags!");
+                // return Err(CPUError::Exit);
+                return Ok(0x20); // Hack :D
             } else if addr == chip_definitions::OSC_STATUS {
                 // HACK: Osci is set right..
                 return Ok(2);
@@ -509,6 +513,22 @@ impl CPU {
                     self.pc += 1;
                 }
             },
+            Instruction::CPSE(ref r, ref d) => {
+                if self.get_register(r) == self.get_register(d) {
+                    // TODO: assume 2b instruction after this one.
+                    self.pc += 1;
+                }
+            },
+            Instruction::MUL(ref r, ref d) => {
+                //  R1:R0 ← Rd × Rr(unsigned ← unsigned × unsigned)
+                let r = self.get_register(r) as u16;
+                let d = self.get_register(d) as u16;
+                let v = r * d;
+                self.registers[0] = (v & 0xFF) as u8;
+                self.registers[1] = ((v >> 8) & 0xFF) as u8;
+                self.set_clear_flag(StatusFlag::Carry, v & 0x80 == 0x80);
+                self.set_clear_flag(StatusFlag::Zero, v == 0);
+            },
             Instruction::NOP => {},
             _ => return Err(CPUError::UnimplementedInstruction)
         }
diff --git a/src/decoder.rs b/src/decoder.rs
index ff86efd..a7f53fc 100644
--- a/src/decoder.rs
+++ b/src/decoder.rs
@@ -107,33 +107,33 @@ pub enum Instruction {
 impl fmt::Display for Instruction {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
         match *self {
-            Instruction::ADC(ref r, ref d) => write!(f, "ADC {} {}", r, d),
-            Instruction::ADD(ref r, ref d) => write!(f, "ADD {} {}", r, d),
-            Instruction::ADIW(ref r, v) => write!(f, "ADIW {} {}", r, v),
-            Instruction::AND(ref r, ref d) => write!(f, "AND {} {}", r, d),
-            Instruction::ANDI(ref r, v) => write!(f, "ANDI {} {}", r, v),
+            Instruction::ADC(ref r, ref d) => write!(f, "ADC {}, {}", r, d),
+            Instruction::ADD(ref r, ref d) => write!(f, "ADD {}, {}", r, d),
+            Instruction::ADIW(ref r, v) => write!(f, "ADIW {}, {}", r, v),
+            Instruction::AND(ref r, ref d) => write!(f, "AND {}, {}", r, d),
+            Instruction::ANDI(ref r, v) => write!(f, "ANDI {}, {}", r, v),
             Instruction::ASR(ref r) => write!(f, "ASR {}", r),
-            Instruction::BLD(ref r, v) => write!(f, "BLD {} {}", r, v),
+            Instruction::BLD(ref r, v) => write!(f, "BLD {}, {}", r, v),
             Instruction::BREAK => write!(f, "BREAK"),
             Instruction::BR_IF(rel, ref flag, tgt) => write!(f, "BR_IF {}, {:?}=={}", rel, flag, tgt),
-            Instruction::BST(ref r, v) => write!(f, "BST {} {}", r, v),
+            Instruction::BST(ref r, v) => write!(f, "BST {}, {}", r, v),
             Instruction::CALL(pc) => write!(f, "CALL {:06X}", pc),
-            Instruction::CBI(ref ior, v) => write!(f, "CBI {} {}", ior, v),
+            Instruction::CBI(ref ior, v) => write!(f, "CBI {}, {}", ior, v),
             Instruction::CLR_FLAG(flag) => write!(f, "CLR_FLAG {:?}", flag),
             Instruction::CLR(ref r) => write!(f, "CLR {}", r),
             Instruction::COM(ref r) => write!(f, "COM {}", r),
-            Instruction::CP(ref r, ref d) => write!(f, "CP {} {}", r, d),
-            Instruction::CPC(ref r, ref d) => write!(f, "CPC {} {}", r, d),
+            Instruction::CP(ref r, ref d) => write!(f, "CP {}, {}", r, d),
+            Instruction::CPC(ref r, ref d) => write!(f, "CPC {}, {}", r, d),
             Instruction::CPI(ref r, v) => write!(f, "CPI {} {}", r, v),
             Instruction::CPSE(ref r, ref d) => write!(f, "CPSE {} {}", r, d),
             Instruction::DEC(ref r) => write!(f, "DEC {}", r),
             Instruction::EICALL => write!(f, "EICALL"),
             Instruction::EIJMP => write!(f, "EIJMP"),
             Instruction::ELPM(ref r, ref mode) => write!(f, "ELPM[{:?}] {}", mode, r),
-            Instruction::EOR(ref r, ref d) => write!(f, "EOR {} {}", r, d),
-            Instruction::FMUL(ref r, ref d) => write!(f, "FMUL {} {}", r, d),
-            Instruction::FMULS(ref r, ref d) => write!(f, "FMULS {} {}", r, d),
-            Instruction::FMULSU(ref r, ref d) => write!(f, "FMULSU {} {}", r, d),
+            Instruction::EOR(ref r, ref d) => write!(f, "EOR {}, {}", r, d),
+            Instruction::FMUL(ref r, ref d) => write!(f, "FMUL {}, {}", r, d),
+            Instruction::FMULS(ref r, ref d) => write!(f, "FMULS {}, {}", r, d),
+            Instruction::FMULSU(ref r, ref d) => write!(f, "FMULSU {}, {}", r, d),
             Instruction::ICALL => write!(f, "ICALL"),
             Instruction::IJMP => write!(f, "IJMP"),
             Instruction::IN(ref r, ref ior) => write!(f, "IN {}, {}", r, ior),
@@ -143,17 +143,17 @@ impl fmt::Display for Instruction {
             Instruction::LAS(ref r) => write!(f, "LAS {}", r),
             Instruction::LAT(ref r) => write!(f, "LAT {}", r),
             Instruction::LD(ref r, ref d, ref mode) => write!(f, "LD {}, [{} {:?}]", r, d, mode),
-            Instruction::LDI(ref r, v) => write!(f, "LDI {} {}", r, v),
-            Instruction::LDS8(ref r, v) => write!(f, "LDS8 {} {}", r, v),
-            Instruction::LDS16(ref r, v) => write!(f, "LDS16 {} {}", r, v),
+            Instruction::LDI(ref r, v) => write!(f, "LDI {}, {}", r, v),
+            Instruction::LDS8(ref r, v) => write!(f, "LDS8 {}, {}", r, v),
+            Instruction::LDS16(ref r, v) => write!(f, "LDS16 {}, {}", r, v),
             Instruction::LPM(ref r, ref mode) => write!(f, "LPM {} {:?}", r, mode),
             Instruction::LSL(ref r) => write!(f, "LSL {}", r),
             Instruction::LSR(ref r) => write!(f, "LSR {}", r),
             Instruction::MOV(ref r, ref d) => write!(f, "MOV {}, {}", r, d),
             Instruction::MOVW(ref r, ref d) => write!(f, "MOVW {}, {}", r, d),
-            Instruction::MUL(ref r, ref d) => write!(f, "MUL {} {}", r, d),
-            Instruction::MULS(ref r, ref d) => write!(f, "MULS {} {}", r, d),
-            Instruction::MULSU(ref r, ref d) => write!(f, "MULSU {} {}", r, d),
+            Instruction::MUL(ref r, ref d) => write!(f, "MUL {}, {}", r, d),
+            Instruction::MULS(ref r, ref d) => write!(f, "MULS {}, {}", r, d),
+            Instruction::MULSU(ref r, ref d) => write!(f, "MULSU {}, {}", r, d),
             Instruction::NEG(ref r) => write!(f, "NEG {}", r),
             Instruction::NOP => write!(f, "NOP"),
             Instruction::OR(ref r, ref d) => write!(f, "OR {} {}", r, d),
@@ -167,15 +167,15 @@ impl fmt::Display for Instruction {
             Instruction::RJMP(rv) => write!(f, "RJMP {:X}", rv),
             Instruction::ROL(ref r) => write!(f, "ROL {}", r),
             Instruction::ROR(ref r) => write!(f, "ROR {}", r),
-            Instruction::SBC(ref r, ref d) => write!(f, "SBC {} {}", r, d),
-            Instruction::SBCI(ref r, v) => write!(f, "SBCI {} {}", r, v),
-            Instruction::SBI(ref ior, v) => write!(f, "SBI {} {}", ior, v),
-            Instruction::SBIC(ref ior, v) => write!(f, "SBIC {} {}", ior, v),
-            Instruction::SBIS(ref ior, v) => write!(f, "SBIS {} {}", ior, v),
-            Instruction::SBIW(ref r, v) => write!(f, "SBIW {} {}", r, v),
-            Instruction::SBR(ref r, v) => write!(f, "SBR {} {}", r, v),
-            Instruction::SBRC(ref r, v) => write!(f, "SBRC {} {}", r, v),
-            Instruction::SBRS(ref r, v) => write!(f, "SBRS {} {}", r, v),
+            Instruction::SBC(ref r, ref d) => write!(f, "SBC {}, {}", r, d),
+            Instruction::SBCI(ref r, v) => write!(f, "SBCI {}, {}", r, v),
+            Instruction::SBI(ref ior, v) => write!(f, "SBI {}, {}", ior, v),
+            Instruction::SBIC(ref ior, v) => write!(f, "SBIC {}, {}", ior, v),
+            Instruction::SBIS(ref ior, v) => write!(f, "SBIS {}, {}", ior, v),
+            Instruction::SBIW(ref r, v) => write!(f, "SBIW {}, {}", r, v),
+            Instruction::SBR(ref r, v) => write!(f, "SBR {}, {}", r, v),
+            Instruction::SBRC(ref r, v) => write!(f, "SBRC {}, {}", r, v),
+            Instruction::SBRS(ref r, v) => write!(f, "SBRS {}, {}", r, v),
             Instruction::SER(ref r) => write!(f, "SER {}", r),
             Instruction::SET_FLAG(flag) => write!(f, "SET_FLAG {:?}", flag),
             Instruction::SLEEP => write!(f, "SLEEP"),
@@ -183,8 +183,8 @@ impl fmt::Display for Instruction {
             Instruction::ST(ref r, ref d, ref mode) => write!(f, "ST [{} {:?}], {}", r, mode, d),
             Instruction::STS8(v, ref r) => write!(f, "STS8 {}, {}", v, r),
             Instruction::STS16(v, ref r) => write!(f, "STS16 {}, {}", v, r),
-            Instruction::SUB(ref r, ref d) => write!(f, "SUB {} {}", r, d),
-            Instruction::SUBI(ref r, v) => write!(f, "SUBI {} {}", r, v),
+            Instruction::SUB(ref r, ref d) => write!(f, "SUB {}, {}", r, d),
+            Instruction::SUBI(ref r, v) => write!(f, "SUBI {}, {}", r, v),
             Instruction::SWAP(ref r) => write!(f, "SWAP {}", r),
             Instruction::TST(ref r) => write!(f, "TST {}", r),
             Instruction::WDR => write!(f, "WDR"),
diff --git a/src/main.rs b/src/main.rs
index 33ce509..0a0fad5 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -40,9 +40,11 @@ fn main() {
             _ => {}
         }
 
+        /*
         if cpu.pc == 0xaea / 2 {
             println!("{}", cpu);
         }
+        */
     }
     println!("{}", cpu);