More instructions

This commit is contained in:
Kevin Hamacher 2018-02-11 02:23:47 +01:00
parent ad2af7a2ec
commit 6470a28ad3

View File

@ -393,7 +393,7 @@ impl CPU {
self.set_register(d, t);
},
Instruction::SUB(ref d, ref r) => {
let t = self.get_register(d) - self.get_register(r);
let t = self.get_register(d).wrapping_sub(self.get_register(r));
let dd = self.get_register(d);
self.set_clear_flag(StatusFlag::Carry, t > dd);
self.set_clear_flag(StatusFlag::Zero, t == 0);
@ -441,6 +441,32 @@ impl CPU {
Instruction::LDS8(ref r, ref addr) => {
self.set_register(r, ram[*addr as usize]);
},
Instruction::LSL(ref r) => {
let v = self.get_register(r);
self.set_clear_flag(StatusFlag::Carry, v & 0x80 == 0x80);
self.set_register(r, v << 1);
self.set_clear_flag(StatusFlag::Zero, (v << 1) == 0);
},
Instruction::ROL(ref r) => {
let v = self.get_register(r);
let c = if self.test_flag(StatusFlag::Carry) { 1 } else { 0 };
self.set_clear_flag(StatusFlag::Carry, v & 0x80 == 0x80);
self.set_register(r, v << 1 | c);
self.set_clear_flag(StatusFlag::Zero, (v << 1) | c == 0);
},
Instruction::LSR(ref r) => {
let v = self.get_register(r);
self.set_clear_flag(StatusFlag::Carry, v & 1 == 1);
self.set_register(r, v >> 1);
self.set_clear_flag(StatusFlag::Zero, (v >> 1) == 0);
},
Instruction::ROR(ref r) => {
let v = self.get_register(r);
let c = if self.test_flag(StatusFlag::Carry) { 0x80 } else { 0 };
self.set_clear_flag(StatusFlag::Carry, v & 1 == 1);
self.set_register(r, v >> 1 | c);
self.set_clear_flag(StatusFlag::Zero, (v >> 1 | c) == 0);
},
Instruction::SBRS(ref r, ref bit) => {
let r = self.get_register(r);
if (r & (1 << *bit)) > 0 {