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28
src/cpu.rs
28
src/cpu.rs
@ -393,7 +393,7 @@ impl CPU {
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self.set_register(d, t);
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},
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Instruction::SUB(ref d, ref r) => {
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let t = self.get_register(d) - self.get_register(r);
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let t = self.get_register(d).wrapping_sub(self.get_register(r));
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let dd = self.get_register(d);
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self.set_clear_flag(StatusFlag::Carry, t > dd);
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self.set_clear_flag(StatusFlag::Zero, t == 0);
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@ -441,6 +441,32 @@ impl CPU {
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Instruction::LDS8(ref r, ref addr) => {
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self.set_register(r, ram[*addr as usize]);
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},
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Instruction::LSL(ref r) => {
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let v = self.get_register(r);
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self.set_clear_flag(StatusFlag::Carry, v & 0x80 == 0x80);
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self.set_register(r, v << 1);
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self.set_clear_flag(StatusFlag::Zero, (v << 1) == 0);
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},
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Instruction::ROL(ref r) => {
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let v = self.get_register(r);
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let c = if self.test_flag(StatusFlag::Carry) { 1 } else { 0 };
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self.set_clear_flag(StatusFlag::Carry, v & 0x80 == 0x80);
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self.set_register(r, v << 1 | c);
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self.set_clear_flag(StatusFlag::Zero, (v << 1) | c == 0);
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},
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Instruction::LSR(ref r) => {
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let v = self.get_register(r);
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self.set_clear_flag(StatusFlag::Carry, v & 1 == 1);
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self.set_register(r, v >> 1);
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self.set_clear_flag(StatusFlag::Zero, (v >> 1) == 0);
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},
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Instruction::ROR(ref r) => {
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let v = self.get_register(r);
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let c = if self.test_flag(StatusFlag::Carry) { 0x80 } else { 0 };
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self.set_clear_flag(StatusFlag::Carry, v & 1 == 1);
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self.set_register(r, v >> 1 | c);
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self.set_clear_flag(StatusFlag::Zero, (v >> 1 | c) == 0);
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},
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Instruction::SBRS(ref r, ref bit) => {
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let r = self.get_register(r);
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if (r & (1 << *bit)) > 0 {
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